566 Rtl Design Jobs - Page 11

Responsibilities: * Collaborate with cross-functional teams on project deliverables. * Develop test plans and cases using Cadence tools. * Ensure RTL designs meet functional requirements through verification.

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. As an FPGA Verification engineer, you will be responsible for designing verification plans, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and have a strong will to drive for solutions. Must have 12 16 yearsof experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like the Ethernet, PCIe, I2C, SPI etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take initiatives. Highly motivated team player with exceptional leadership capability. Develop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications. Design and implement simulation environments and testbenches to validate FPGA functionality and performance. Create and run functional and directed/random test scenarios to ensure comprehensive design coverage. Perform detailed coverage analysis and implement strategies to achieve full functional and code coverage. Collaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle. Provide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality. Independently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals.

Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/SystemVerilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering or related fields. 3-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment.

FPGA Developer --> --> Location, Designation --> LocationRemote DesignationFPGA Developer Experience7- 9 Years Skills required: 1. Should have worked on USRP N310/X310 (N3xx/X3x0) 2. In-depth Knowledge of FPGA Architecture 3. Able to write own RTL custom HDL or drops in IP a) VHDL, Verilog, System,Verilog, Vivado HLS b) Xilinx IP, Vivado Block Diagram 4. Should have developed RFNoC Block 5. Have working knowledge of USRP Hardware Driver (UHD) 6. Able to write custom FPGA logic in RFNoC Blocks 7. Able to use library of existing RFNoC Blocks a) FFT, FIR, Signal Generator, Fosphor 8. Have understanding of GNU Radio interface to RFNoC Block 9. FPGA debugging and HW/SW integration 10. Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed 11. In-depth knowledge of XILINX ZYNQ 71xx/pl-kINTEX-7 based RFNoC architecture is must. 12.Understand Customer requirements, define architecture and detailed design 13. Good Customer Communication Skills 14. Working knowledge of Agile Feel Free To Contact Us...!!! Submit

We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Roles & Responsibilites. Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications. Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 6+ years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

CATIA V6 Working Experience on Using CATIA V6 & PLM application. Experience in Wheels ,Tyres & Braking System Stellantis know-how Synthesis and verification of the necessary input data/documents. Develop supplier consultation files (Int/Ext) for a 'complex' component in series production or a 'simple/complex' component purchased as part of a new PTF or new vehicle, or a 'simple/complex' component in development Manage the BE Formalization of consultation documents for a 'complex' component in series production or a 'simple/complex' component purchased as part of a new PTF or new vehicle, or a 'simple/complex' component in development Supplier management (including new) Technical reviews Management of the Development Schedule Management of the Organic and Subsystem Digital and Physical Validation Plan Management of quality/Risk convergence Project Reporting Use of CAD software or other specific software Contribute the QCDP synthesis of the component/Capitalization

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies)

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

Job Description: We are looking for a RTL Design Engineer with expertise in SoC and IP-level design and integration. The ideal candidate should have a strong background in RTL coding, architecture-level understanding, and industry-standard quality checks and tools. Key Responsibilities: Develop RTL code in Verilog/SystemVerilog Understand and apply top-level SoC architecture concepts Perform SoC and IP-level integration Implement RTL quality checks including CLP (mandatory), LINT, CDC, RDC, VSI Work on design partitioning (Tilification) Handle IORING, PHYs, GPIOs Collaborate with verification and backend teams Required Skills: RTL coding in Verilog and SystemVerilog IPXACT knowledge Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) UPF and SDC concepts Tools: VC_static, SpyGlass (Lint, CDC, RDC), 0in, Formality, Conformal LEC Scripting: Perl, Python, TCL Nice to Have: Experience with design quality metrics and standards Exposure to physical-aware RTL design

• Design Methodology, Micro-architecture, RTL. • Work with the architecture team to develop the uArch & Subsequently write RTL. • Develop Design Methodology, starting with the machine learning architecture. • Synthesis, STA, Equivalence checking. Required Candidate profile * EXP in SOC design methodology, Micro-architecture, Emulation & back-end DEV., & Chip Bring-up. * EXP in Developing ARM CPU based SoCs, Network-on-Chip & interfaces such as MIPI-CSI, Ethernet & PCIe

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills and Experience DV Engineer, Design Verification, Verification Engineer

Experience : 3 to 10 Years Qualification : Bachelors or Masters (Electronics and Communication Engineering or equivalent) Job Description: As an Emulation Engineer, youll be an integral part of a dynamic team dedicated to creating cutting-edge ASIC solutions for High-Performance Computing (HPC) systems. Your role will involve defining the validation strategy leading to functional sign-off for these high-performance computing designs. Key functions and responsibilities: Proficient in various emulation technologies, including simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods. Familiarity with tools such as Palladium, Protium, Veloce, or Zebu. Good Knowledge of SystemC/C/C++ and UVM/SV verification languages Experience with SystemVerilog and C++ for modelling RTL components and transactors. Ability to develop C/C++/SystemC/SV tests in HDL-HVL (Hardware Description Language-Hardware Verification Language) Co-emulation platforms. Understanding of compilation and build flow. Skilled at building images from scratch, making necessary design modifications to adapt to emulation. Work closely with verification teams to define and implement comprehensive pre and post silicon test plans. Interface effectively with design, verification, validation, and software development teams to understand their needs from an emulation perspective. Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip systems). Balancing performance and ease of debug. Proficient in post-silicon bring-up, debugging, and issue reproduction on emulators. Familiarity with Python and TCL scripting languages. Exposure to domains such as PCIe, CXL, DDR, Flash, Memory, USB, and CPU. Strong communication and collaboration skills to work effectively with cross-functional teams and domain experts. Successfully manage multiple design releases and provide support for debugging customer issues.

SMTS SILICON DESIGN ENGINEER PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 13+ years of relevant experience Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges Circuit timing/STA, and practical experience with tools Working knowledge of C; embedded experience a plus Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards Been exposed to memory controller and PHYs from different IP vendors Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software Version control systems such as Perforce, ICManage or Git Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. Will be focusing on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for ASIC projects. Work closely with cross-functional teams to deliver high-quality and efficient SoC (System on Chip) designs. This role requires good knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in RTL design and digital logic design. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies Familiarity with verification methodologies (UVM, System Verilog), testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Familiarity with high-level synthesis (HLS) tools Knowledge of scripting languages such as Python, Tcl, or Perl for automation Develop RTL designs using VHDL/Verilog for ASIC projects Perform digital logic design, synthesis, and timing analysis Conduct linting and static analysis to ensure code quality Develop and implement verification methodologies (UVM, System Verilog) Create and maintain testbenches for simulation and functional coverage Perform simulations and debugging to ensure design correctness Participate in design reviews and provide feedback to improve design quality

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: SoC RTL Integration Engineer Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Primary Responsibilities:- Lead complex SoC integration efforts, including the development of top-level architecture and interconnect fabric Design and implement critical integration components such as clock/power distribution networks, reset controllers, and system-level arbitration Resolve sophisticated interface compatibility issues between IP blocks from various sources Develop and maintain comprehensive integration verification strategies Collaborate with IP teams to ensure seamless integration of all subsystems Perform thorough clock domain crossing (CDC) and power domain crossing (PDC) analysis Drive timing closure at the integration level in coordination with physical design teams Implement and optimize system-level power management schemes Lead design reviews and provide technical guidance to junior integration engineers Develop technical specifications for SoC-level integration requirements Required Technical Skills:- 7+ years of RTL design experience with 4+ years focused on SoC integration Expert knowledge of industry-standard bus protocols (AXI, AHB, APB, etc.) Proven experience with large-scale integration challenges in complex SoCs Strong understanding of clock synchronization strategies and metastability management Deep knowledge of power management techniques and implementation Experience with integration-specific verification methodologies Proficiency in debugging complex system-level issues Advanced understanding of timing analysis and constraints at the integration level Advanced Capabilities: Ability to identify and address system-level bottlenecks affecting performance Experience optimizing interconnect architectures for bandwidth and latency requirements Knowledge of security isolation requirements for modern SoCs Skill in balancing conflicting requirements from multiple IP teams Experience mentoring junior engineers on integration methodologies Ability to influence architectural decisions based on integration considerations At the MTS level, you would be expected to independently lead major integration efforts, serve as a technical authority on integration challenges, and contribute to architectural decisions that affect the entire SoC design. TekWissen Group is an equal opportunity employer supporting workforce diversity.

We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Roles & Responsibilites. Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications. Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 2-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

Here is the revised job description with bullets and bolded subheadings: Position and Experience We are seeking a Senior CAD Engineer with 10+ years of experience . Immediate joiners with a notice period of 15 days or less are preferred. Key Responsibilities Deploy and support front-end tools such as RTL simulators, low power tools , and static RTL checkers . Develop scripts to automate regression/debug flows . Manage CI/CD processes . Interface with EDA vendors . Support global teams across geographies. Required Skills Proficiency in scripting (Python, Bash, Make) . Linux system administration . Version control tools (Git, Mercurial) . Experience in ASIC flows and standard CAD tools .

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Position Name :SoC RTL Integration Engineer Position type: Permanent Total Exp: 6-8 years HBTS Budget: Open Notice Period: Immediate to 30days Work Location: Bangalore Job Description Must have: ead complex SoC integration efforts, including the development of top-level architecture and interconnect fabric *Design and implement critical integration components such as clock/power distribution networks, reset controllers, and system-level arbitration *Resolve sophisticated interface compatibility issues between IP blocks from various sources *Develop and maintain comprehensive integration verification strategies *Collaborate with IP teams to ensure seamless integration of all subsystems *Perform thorough clock domain crossing (CDC) and power domain crossing (PDC) analysis *Drive timing closure at the integration level in coordination with physical design teams *Implement and optimize system-level power management schemes *Lead design reviews and provide technical guidance to junior integration engineers *Develop technical specifications for SoC-level integration requirements Required Technical Skills:- *7+ years of RTL design experience with 4+ years focused on SoC integration *Expert knowledge of industry-standard bus protocols (AXI, AHB, APB, etc.) *Proven experience with large-scale integration challenges in complex SoCs *Strong understanding of clock synchronization strategies and metastability management *Deep knowledge of power management techniques and implementation *Experience with integration-specific verification methodologies *Proficiency in debugging complex system-level issues *Advanced understanding of timing analysis and constraints at the integration level Advanced Capabilities: *Ability to identify and address system-level bottlenecks affecting performance *Experience optimizing interconnect architectures for bandwidth and latency requirements *Knowledge of security isolation requirements for modern SoCs *Skill in balancing conflicting requirements from multiple IP teams *Experience mentoring junior engineers on integration methodologies *Ability to influence architectural decisions based on integration considerations At the MTS level, you would be expected to independently lead major integration efforts, serve as a technical authority on integration challenges, and contribute to architectural decisions that affect the entire SoC design. AMD (Dont Share AMD Profiles) Preferred candidate profile

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Industry: SEMICON Position Name RTL Design Lead/uArch/Design Engineer Position type: Permanent Total Exp: 10-15 years HBTS Budget: Open Notice Period: Immediate to 15days Work Location: Bangalore Job Description Must have: We're looking for a highly skilled RTL Design Lead to lead our digital design team. The successful candidate will be responsible for designing, developing, and verifying complex digital circuits using RTL design methodologies. The RTL Design Lead will work closely with cross-functional teams to ensure seamless integration of digital design blocks into larger systems. Key Responsibilities: 1. Lead a team of RTL designers to design, develop, and verify complex digital circuits. 2. Develop and maintain RTL design methodologies, standards, and best practices. 3. Collaborate with architects to define and implement digital architecture. 4. Work closely with verification teams to ensure seamless integration of digital design blocks. 5. Participate in design reviews, provide feedback, and ensure design quality. 6. Develop and manage project schedules, resource allocation, and budgets. 7. Mentor and train junior designers to improve team capabilities. Requirements: 1. Bachelor's/Master's degree in Electrical Engineering, Computer Science, or related field. 2. 10+ years of experience in RTL design, with at least 3 years in a RTL design/uArch leadership role. 3. Strong expertise in digital design principles, RTL design methodologies, and verification techniques. 4. Proficiency in HDLs (Verilog/SystemVerilog/VHDL), design tools (e.g., Synopsys, Cadence), and scripting languages (e.g., Perl, Python). 5. Excellent leadership, communication, and project management skills. 6. Strong problem-solving skills, with the ability to analyze complex design issues. Nice to Have: 1. Experience with ASIC/FPGA design flows. 2. Knowledge of computer architecture, microprocessors, and embedded systems. 3. Familiarity with industry-standard design methodologies (e.g., OVM, UVM). 4. Certification in RTL design or related field. AMD (Dont Share AMD Profiles) Preferred candidate profile

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: Key Responsibilities: Understand RTL at structural level, IP boundaries, IP parameters. Understand IP design. Add assertions where needed. Generate various constraints necessary for the IP. RTL build flow setup and maintenance. Do the quality checks of the IP like Lint/CDC/RDC/Synth/Timing checks/waiver creation across milestones. Participate in IP integration to the subsystem level. Write sample test bench to verify the basic functionality of the IP/block. Do the first level of triage of the functional issues reported. Understand the reports out of quality checks such as Lint/CDC/RDC/Synth/Timing checks and suggest fix in the RTL Work with functional verification team to meet coverage and quality standards. Guarantee quality/timely deliverables meeting projects schedule. Help to improve/automate design process. PREFERRED EXPERIENCE: Knowledge of ASIC development flows Knowledge of front-end RTL design tools and methodologies. Knowledge of system Verilog Multi-clock domain designs. Design constraints for synthesis and static timing analysis. Experience in RTL linting tools, reset domain crossings, clock domain crossings, synthesis, RAM generation (area, timing, power) Knowledge of AXI/AMBA protocol Ability to create a simple SV based Test benches, create sanity test plan, run the test cases Knowledge of front-end requirements and deliverables for verification, validation, physical design, architecture, security, dfx, power. Verification - coverage, test plan, debug Physical design – timing, clock crossings, reset crossings, ECOs (manual, formal) Ability to work and effectively collaborate with partners Knowledge of scripting languages like Perl, tcl or cshell Experience with DMAs, PCIe, ordering, data path virtualization, performance, flow control a plus. TekWissen® Group is an equal opportunity employer supporting workforce diversity.

1+ Yrs Experience working on modern front-end web technologies, including: React, JS(ES6+) TypeScript, Next.js, HTML5, CSS3 and Less/Sass ability to write mixins, partials, functions, etc developing highly-optimized applications using React and Redux Required Candidate profile Experience interning in the E-Commerce Experience with the standard tooling Webpack, Babel, Linting, JS Typing, and Prettier. Experience in Caching

We are looking for a highly experienced Senior CAD Engineer to join our team in Bangalore. The ideal candidate will be responsible for deploying and supporting front-end design tools, developing automation scripts, and managing CI/CD workflows across global teams. Key Responsibilities: Deploy, maintain, and support front-end EDA tools, including: RTL simulators Low power analysis tools Static RTL checkers Develop and maintain automation scripts for: Regression testing Debug flows Manage and optimize CI/CD pipelines for front-end development and verification environments. Collaborate with EDA vendors for tool support, licensing, and enhancements. Provide technical support to design teams across multiple global locations. Perform basic Linux system administration and manage user environments. Required Skills and Experience: 10+ years of experience in CAD engineering, especially with front-end tool flows. Strong scripting abilities in Python, Bash, and Make. Proficient in Linux system administration for CAD tool environments. Hands-on experience with version control systems such as Git or Mercurial. Solid understanding of ASIC design flows and standard CAD tools from major EDA vendors (e.g., Synopsys, Cadence). Excellent problem-solving, communication, and cross-functional collaboration skills. Preferred Qualifications: Candidates with a notice period of 15 days or less. Experience working in global engineering teams and managing multi-site tool environments.

We are seeking an experienced Senior CAD Engineer to join our team in Bangalore. The ideal candidate will play a critical role in deploying, automating, and supporting front-end CAD tools and flows for global hardware development teams. Key Responsibilities: Deploy and provide support for front-end tools, including: RTL simulators Low power analysis tools Static RTL checkers Develop and maintain scripts to automate regression, debug flows, and other repetitive tasks. Manage and optimize CI/CD processes for design and verification environments. Collaborate and interface with EDA vendors for tool support, issue resolution, and license management. Work closely with global engineering teams across geographies to provide consistent CAD tool support. Maintain and administer Linux systems used in design environments. Required Skills and Experience: 10+ years of experience in CAD engineering, particularly in front-end digital design flows. Strong scripting skills: Python, Bash, Makefiles, etc. Hands-on experience in Linux system administration. Proficiency in version control tools such as Git or Mercurial. Solid understanding of ASIC design flows and experience with standard CAD tools (e.g., Synopsys, Cadence). Ability to manage tool deployment, automation, and support in a multi-site, global environment. Strong communication skills and a proactive, problem-solving mindset. Preferred: Candidates with a notice period of 15 days or less.

Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl signoff tools, upf/low power signoff and cdc/rdc, lint Strong domain knowledge of clocking, system modes. Power management, debug, interconnect, safety, security and other architectures