560 Rtl Design Jobs - Page 8

Qualcomm India Private Limited is a leading technology innovator that aims to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. The ideal candidate should possess strong analytical and technical skills, especially in ASIC design. Responsibilities for this position include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be expected to create design experiments, conduct detailed PPA comparison analysis, collaborate with various teams for optimization, and develop Place & Route recipes for optimal PPA results. Qualifications required for this role include 6-15 years of experience in High-Performance core Place & Route and ASIC design Implementation. Preferred qualifications involve extensive experience in Place & Route with FC or Innovus, knowledge of complete ASIC flow with optimization techniques, proficiency in STA using Primetime and/or Tempus, and skills in Perl/Tcl, Python, C++, among others. Problem-solving abilities, experience with CPU micro-architecture, low power implementation techniques, and clock tree implementation techniques are also desired. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If accommodation is needed during the application/hiring process, individuals can contact Qualcomm for support. The company expects its employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised that only individuals seeking a job at Qualcomm should use the Careers Site. Unsolicited submissions from agencies will not be accepted. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

Qualcomm India Private Limited is a company of inventors at the forefront of 5G technology, unlocking new possibilities that will revolutionize industries, create job opportunities, and enhance lives. As part of the Engineering Group in the Hardware Engineering division, you will be joining a dynamic team responsible for designing Low Power controller IP cores and subsystem digital design for cutting-edge Snapdragon SoCs used in mobile, compute, IoT, and Automotive markets globally. In this role based at Qualcomm's Bangalore office, your key responsibilities will include micro-architecture and RTL design for Cores/subsystems, collaborating closely with Systems, Verification, SoC, SW, PD & DFT teams, enabling software teams to utilize hardware blocks, qualifying designs through static tool checks, and reporting progress status against expectations. Preferred qualifications for this position include 5 to 10 years of experience in digital front-end design (RTL design) for ASICs, expertise in RTL coding in Verilog/SV/VHDL, familiarity with UPF and power domain crossing, experience in synthesis, logical equivalence checks, RTL and netlist CLP, proficiency in various bus protocols, low power design methodology, clock domain crossing designs, formal verification, and database management flows. Additionally, expertise in Perl/TCL/Python language, post-Si debug, and strong communication skills are valued qualities for this role. To be considered for this opportunity, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 4+ years of Hardware Engineering experience, or a Master's degree with 3+ years of relevant work experience, or a PhD with 2+ years of related work experience. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities during the application/hiring process. Please reach out to disability-accommodations@qualcomm.com for support. The company expects its employees to comply with all applicable policies and procedures, including confidentiality requirements. If you are a staffing or recruiting agency, please note that Qualcomm's Careers Site is exclusively for individual job seekers, and submissions from agencies will be considered unsolicited. For more information about this role, please contact Qualcomm Careers directly.,

Roles and Responsibility Senior IO-MMU Design Engineer Role Overview: Leads the design and integration of IO Memory Management Units (IO-MMUs) for secure, virtualized, and high-performance SoC architectures. Key Responsibilities: Architect and implement RTL for IO-MMU subsystems Define IO translation and access control logic Collaborate with SoC, interconnect, and virtual memory teams Ensure compliance with IOMMU standards (SMMU, PCIe ATS/PRI, RMRR) Deliver Lint, CDC, synthesis, and DFT clean designs Required Skills: 8+ years of experience in SoC and IP-level RTL design Strong in SystemVerilog, with knowledge of memory protection and address translation Experience with SoC virtual memory systems and PCIe/AXI protocols Familiar with coherency, TLB, page walk and IOVA mechanisms Skilled in timing closure and formal/CDC tools

Hiring now Criteria - B.Tech below 2022 and M.Tech below 2024 Location - Bangalore Preferred Engineers who have completed their Training in #VLSI domains for below requirements #PD #AL #RTL #DFT Share profiles to kartikchandu@juntrantech.com Health insurance Provident fund

Job Title: RTL Design Engineer Work Mode: Hybrid Location: Noida Job Description • Work together with system architects and micro architects to define high level specifications that are implementable. • Contribute to RTL development including running tool flows like lint, CDC, Conformal low power and DFT checks • Work closely with functional verification teams on test-plan development and debug. • Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. • UPF writing, power aware equivalence checks and low power checks. • Collaborate with other functional teams including DFT, physical design and emulation teams to achieve project milestones. • Provide support to functional validation teams in post silicon debug. Qualifications • MTech/BTech in EE/CS with hardware engineering experience of 1 to 15 years. • Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low- power checks, etc.), synthesis/DFT/FV/STA • Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency. • Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. • Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. • Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. • Experience with post-silicon bring-up and debug is a plus. • Able to work with teams across the globe and possess good communication skills

Key Responsibilities: Collaborate on ASIC backend design activities including synthesis, place-and-route, timing analysis, and physical verification. Develop and optimize design flows using EDA tools (e.g., Synopsys, Cadence, Mentor). Perform static timing analysis (STA) and fix timing violations to meet design constraints. Conduct signal integrity analysis, power analysis, and floorplanning. Work with RTL designers to optimize designs for manufacturability and performance. Generate design documentation, scripts, and reports to support ASIC development. Support debugging and silicon validation activities. Participate in design reviews, sign-off processes, and tape-out preparation. Qualifications and Requirements: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in ASIC backend design or physical design. Proficiency with ASIC EDA tools (e.g., Synopsys Design Compiler , IC Compiler , PrimeTime , Cadence Innovus ). Strong knowledge of ASIC design flow, timing closure, and verification. Experience with scripting languages (TCL, Perl, Python) for automation. Understanding of semiconductor process technologies and constraints. Excellent problem-solving and communication skills. Desirable Skills: Experience with low-power design techniques and methodologies. Familiarity with DFT (Design for Test) insertion and ATPG tools. Knowledge of mixed-signal ASIC design is a plus. Exposure to RTL design and verification flows. Experience with FPGA prototyping and emulation.

Qualcomm India Private Limited is a leading technology innovator that is committed to pushing the boundaries of what's possible. We strive to enable next-generation experiences and drive digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year of Hardware Engineering or related work experience. Qualcomm is currently hiring for multiple roles in the following domains: 1. Physical Design 2. RTL Design 3. Design Verification 4. STA/Synthesis 5. DFT 6. FPGA Emulation 7. Validation Qualcomm is an equal opportunity employer that is committed to providing accommodations for individuals with disabilities during the application/hiring process. If you require an accommodation, you can email disability-accommodations@qualcomm.com or call the toll-free number provided on our website. Reasonable accommodations will be provided upon request to support individuals with disabilities in participating in the hiring process. Our workplace is designed to be accessible for individuals with disabilities. Employees at Qualcomm are expected to adhere to all applicable policies and procedures, including those related to security and the protection of confidential information. This extends to safeguarding Company confidential information and other proprietary information in accordance with applicable laws. For Staffing and Recruiting Agencies: Our Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not authorized to use this site or submit profiles, applications, or resumes. Any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Kindly refrain from forwarding resumes to our jobs alias, Qualcomm employees, or any other company location. Qualcomm will not be responsible for any fees related to unsolicited resumes or applications. For more information about the available roles, please reach out to Qualcomm Careers.,

Since June 2021, frog is part of Capgemini Invent . frog partners with customer-centric enterprises to drive sustainable growth, by building and orchestrating experiences at scale, while harnessing the power of data and technology. Were inventing the future of customer experiences by delivering market-defining business models, products, services, brand engagements and communications. Joining frog means youll be joining the pond, a global network of studios, each with a thriving in-person and vibrant virtual culture. frogs are curious, collaborative, and courageous, united by our passion for improving the human experience across our areas of expertise, while each bringing our unique and diverse skills and experiences to the table. We draw on our global reach and local knowledge to solve complex problems and create innovative, sustainable solutions that touch hearts and move markets. frogs prize humour, positivity, and community just as highly as performance and outcomes. Our culture is open, flexible, inclusive, and engaging. Working at frog means being empowered to meet the moment, and Make Your Mark on every project, in your studio, your community and the world at large. Equal Opportunities at frog Frog and Capgemini Invent are Equal Opportunity Employers encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status, or any other characteristic protected by law.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Design Engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: Worked for ASIC/SOC RTL Integration for at least 1 year in actual customer project. Worked for analyzing/debugging ASIC/SOC CDC/RDC violations for at least 1 year in actual customer project. Worked for debugging timing issues or CLP issues and fixes for 6 months-1 year Must be above average in digital design fundamentals Good debugging skills are a mandate. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Key Responsibilities: Hands-on microarchitecture and RTL development for IP blocks Develop microarchitecture based on design specifications, including HW-SW interface definition IP-level verification and debugging for video and audio subsystems Work on MIPI CSI and DSI protocols understanding at protocol and implementation level Collaborate with design, verification, and software teams to ensure high-quality deliverables Drive or contribute to test plan creation, environment development, and coverage closure

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on a wide range of components such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is key to developing solutions that meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 3 years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with a minimum of 2 years of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 1 year of Hardware Engineering or related work experience. We are currently hiring for multiple roles in the following domains: 1. Physical Design 2. RTL Design 3. Design Verification 4. STA/ Synthesis 5. DFT 6. FPGA Emulation 7. Validation Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodation during the application/hiring process, please contact disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. Employees at Qualcomm are expected to adhere to all applicable policies and procedures, including those related to security and confidentiality. The company is dedicated to making the workplace accessible for individuals with disabilities. To Staffing and Recruiting Agencies: Our Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing agencies and represented individuals are not authorized to submit profiles, applications, or resumes through this site. Unsolicited submissions will not be accepted, and Qualcomm does not acknowledge fees related to unsolicited resumes/applications. For further information about available roles, please reach out to Qualcomm Careers.,

As a SoC RTL Design Engineer at Lattice Semiconductor, you will join the HW design team focused on IP design and full chip integration. This exciting position offers the opportunity to be part of a dynamic team where you can contribute, learn, innovate, and grow. Located in Pune, India, this full-time role will concentrate on RTL design, full chip integration, and projects within similar time zones, providing ample opportunities to work on cutting-edge technologies. Your responsibilities will include working on RTL design with best-in-class coding styles, algorithms, and utilizing Verilog and System Verilog. You will also be involved in SoC integration and quality checks such as lint, CDC, RDC, SDC, etc. Collaborating closely with the architect and micro-architect team, you will define design specifications and work towards accelerating design time and improving quality through logic design of key blocks and full chips. To be successful in this role, you should have a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science, or equivalent, along with at least 5 years of experience in driving logic design across various silicon projects. Expertise in SoC integration, defining micro-architecture, and experience with 3rd party IP selection is required. Additionally, familiarity with FPGA designs, ARM processor, AXI, AMBA bus, ENET, PCIE, safety and security protocols, and debug architecture will be advantageous. You should be an independent worker and leader with strong problem-solving abilities, capable of working with multiple groups across different sites and time zones. Occasional travel may be required as part of the role. Lattice Semiconductor values its employees and offers a comprehensive compensation and benefits program to attract, retain, and reward top talent in the industry. Lattice Semiconductor is a service-driven developer of innovative low-cost, low-power programmable design solutions with a global workforce that is dedicated to customer success and driven to achieve excellence. If you are passionate about working in a fast-paced, results-oriented environment and believe you can thrive in a demanding yet collegial atmosphere, Lattice Semiconductor may be the perfect fit for you. Feel the energy at Lattice Semiconductor.,

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Bengaluru. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come We make real what matters! This is your role Deploy Siemens EDA ProFPGA prototyping software and hardware solutions at customers and guide the customers to successful design bring-up Work closely with R&D to solve problems, review product specs, and find good general solutions that improve the overall product Train AE’s and customers on the solutionWin pre-sales engagements in cooperation with the technical sales teams Successfully deploy our solutions at early customer sites. This means educating the customer on best practices and tool requirements. It also means working with R&D to make the tool improvements necessary for the customer’s success. Ensure existing customers maximize the value they receive from the solution by developing and enhancing methodology that exploits the solution’s capabilities Ensure customers are kept up-to-date with the latest enhancements Provide customer requirements to R&D and marketing Work with QA and Docs to help them create tests and documentation that will improve our solutions Create examples and tutorials that are shipped with our products. Develop and/or refine methodology employed in creating and using prototypes and maximizing the value of our prototyping solution We don’t need superheroes, just super minds! A good understanding of FPGA based hardware prototyping platforms Working knowledge of multi FPGA prototyping flows(Synthesis, partitioning, PnR, runtime and debug) Practical insights into the application and usage of FPGA prototyping systems Knowledge of design mapping, testbench mapping and transactor development Expertise of hardware/software debug solutions related to FPGA prototyping Knowledge of test bench acceleration, ICE and co-model solutions Highly proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification Solid background in Functional Verification, RTL synthesis and PnR flows Conversant with SoC design and architecture concepts Good communication and inter-personal skills. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Where today meets tomorrow #LI-EDA #LI-Hybrid

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Required technical and professional expertise -2+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Role & responsibilities We are seeking a highly motivated RTL Design Engineer with 7-12 years of experience to join our growing team. You will play a vital role in the design and development of complex digital logic for next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in RTL design methodologies and verification. Responsibilities: Design and develop RTL code for digital logic blocks and modules using Verilog or VHDL Perform comprehensive functional verification using industry-standard methodologies (e.g., UVM) Conduct static timing analysis (STA) and participate in timing closure activities Integrate designed modules into larger subsystems and ensure seamless functionality Collaborate effectively with design, verification, and synthesis teams throughout the development cycle Write clear, concise, and well-documented RTL code adhering to coding standards Stay current with advancements in RTL design tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-12 years of solid experience in RTL design for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to design and verify high-performance and efficient digital circuits Expertise in Verilog or VHDL with a strong understanding of coding styles and best practices Experience with simulation and verification tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) Familiarity with SDC (Standard Delay Constraint) format for timing analysis Excellent problem-solving skills and a meticulous attention to detail Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement

FPGA/RTL DESIGN ENGINEER (4 to 10 Years) FPGA Design Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune] Experience: 4 to 10 Years Openings: 2 Positions Preference - Immediate to 45 Days Job Description Responsibilities Design, implement, and validate FPGA architectures and digital circuits, ensuring high performance and reliability. Utilize VHDL/Verilog to develop and simulate complex digital systems, optimizing for speed and resource utilization. Collaborate with cross-functional teams to define requirements, specify design parameters, and conduct design reviews. Conduct thorough testing and debugging of FPGA designs, employing tools such as ModelSim, Vivado, and SignalTap. Document design processes and methodologies, maintaining detailed records for compliance and future reference. Stay abreast of industry trends and emerging technologies to continuously enhance design practices and methodologies. Required and Preferred Qualifications Required: Bachelor's degree in electrical engineering, Computer Engineering, or a related field. 4+ years of experience in FPGA design, with a proven track record of successful project delivery. Strong proficiency in VHDL/Verilog and experience with FPGA development tools such as Xilinx Vivado or Intel Quartus. Solid understanding of digital design principles, including timing analysis, signal integrity, and data path optimization. Preferred: Master's degree in a relevant field. Experience with high-speed design and mixed-signal circuits. Familiarity with hardware description languages for system-level design. Knowledge of embedded systems and experience with microcontroller/Microprocessor interfaces. Technical Skills and Relevant Technologies Expertise in FPGA architecture and design tools (Xilinx, Intel, Lattice). Experience with simulation and verification tools (ModelSim, Questa, etc.). Strong knowledge of digital signal processing (DSP) concepts and applications. Soft Skills and Cultural Fit Exceptional problem-solving abilities with a keen attention to detail. Strong collaboration and communication skills, with the ability to work effectively in a team environment. Proactive approach to identifying opportunities for improvement and innovation. Passionate about technology, with a continuous learning mindset.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT.: Experience: 3-5 Years.

Job Title: VLSI Engineer (Academic Role Teaching Computer Architecture) Location: Rishihood University, Sonipat (On-site) Type: Full-Time | Immediate Joiners Preferred Experience: 37 years Department: Engineering & Technology | Academic Instruction About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are builtfrom logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities: Teach Computer Architecture by drawing from real-world VLSI design experience—covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Must-Have Skills & Qualifications: B.Tech / M.Tech / Ph.D. in Computer Engineering , Electronics , Electrical , or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence , ModelSim , Synopsys , Xilinx , Mentor Graphics , etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting ( Tcl , Shell , Python ). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V , ARM-based processors, SoC Design, or low-power systems. Exposure to DFT , verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats. Why Join Us? Work at the intersection of deep tech and academia in a modern, innovation-led learning environment. Influence curriculum and pedagogy at a forward-thinking institution backed by Newton School of Technology and Rishihood University . Collaborate with a team of industry leaders and passionate educators in building India’s next generation of engineers.

The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT. Experience: 3-5 Years.

Responsibilities: * Develop RTL designs using Verilog, * Collaborate on ASIC projects from concept to delivery. * Ensure design compliance with industry standards. For fast response Share to mansoor@hisoltech.com

Our vision is to transform how the world uses information to enrich life for . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we transform how the world uses information to enrich life for all. The pace is fast, collaboration occurs on a regular basis, and innovation is expected. As a test platform development Engineer within the Non-Volatile Engineering (NVEG) Product Engineer team, you will develop and qualify low-cost in-house engineering test platforms and solve complex problems. This role requires deep understanding of test hardware and software along with NAND, UFS and PCIe protocol knowledge. You will be responsible to enable the PE test infrastructure and test platforms to test, debug and characterizing the NAND component and System products by closely working with the cross functional teams such as Test Engineering and System Integration, ASIC and FW teams and assist Qualification and Ramping of cutting-edge NAND and System Micron products. The candidate's responsibility is to design, develop and debug the VHDL or Verilog based application and have good knowledge of FPGA platform development lifecycle. Key Responsibilities: Design, develop, and qualify product engineering test hardware, platforms, test firmware and software for non-volatile memory product bring up and debug. Develop efficient RTL design using Verilog or VHDL for FPGA implementation, ensuring optimal resource utilization. Drive complete FPGA design flow including synthesis, place and route, timing analysis and verification. Implement FPGA designs on hardware platforms using tools like Xilinx Vivado and optimize for performance, area and power and to create test bench and verification scripts. Debug and validate FPGA designs in hardware using tools such as oscilloscopes , logic analyzers , and signal tap . Optimize designs for speed, power, and resource usage based on the specific FPGA platform used. Collaborate with cross-functional teams, including Test Engineering & System Integration, ASIC, FW, Product Engineering and operations, to integrate FPGA designs with other system components. Provide engineering test solutions (HW & SW) for Product Development for NAND/System characterization and Silicon debug capabilities Drive and support new protocol enablement (SCA- Separate Command Address, ONFI, UFS, PCIe) and capability bring up Routinely communicate overall project status to leadership and cross functional product team Provide guidance through debug and resolution of product related issues Qualifications: Successful candidates for this exciting opportunity will have: 6+ years of experience in RTL design, synthesis, timing closure, and verification methodologies. Knowledge of storage interface such as High Speed ONFI, UFS, PCIe, etc. Memory and Storage System behavior, architecture and design Working experience on NAND and non-volatile System products Experience with non-volatile memory, logic analyzers, oscilloscopes, and/or Automated Test Equipment (ATE) is preferred Experience working on firmware development using C/C++ and good understanding of scripting languages including TCL, Perl/Python. Familiar working on Unix/Linux terminal. Hands-on experience with hardware bring-up and debugging and Understanding of hardware schematic and layout. Excellent data analysis, problem solving, and decision-making skills Ability to work independently in a very fast paced environment and adapt to change Drive to determine root-cause and provide corrective action for product issues Self-motivated and enthusiastic in a challenging, dynamic environment Demonstrated ability to partner successfully with other groups to build strong peer relationships and achieve the best outcomes for Micron Education: Position requires a minimum of a Bachelor's degree in Electrical, Electronics or Computer Engineering Course work in VLSI, semiconductor process is desirable, but not required

As a member of AMD's CPU Performance Validation team in Bangalore, you will play a crucial role in the design of next-generation AMD CPUs. Your responsibilities will include gaining a deep understanding of AMD X86 CPU architecture and microarchitecture, debugging performance issues in RTL, and providing feedback to the design team for the latest CPU generation in pre-silicon and emulation environments. We are looking for individuals with a creative mindset and a natural inclination to delve into details. This team is ideal for those who can grasp the present while envisioning the future. If you are someone who is willing to go the extra mile to refine existing processes and possesses innovative ideas waiting to be realized, this is the perfect opportunity for you. Your success in this role will be supported by excellent interpersonal and communication skills, along with the ability to thrive in a fast-paced and dynamic environment. Continuous learning is essential in this ever-evolving industry, and as such, self-improvement and skill enhancement are highly valued traits. Collaboration, learning, and sharing knowledge within the team are pivotal to our collective growth and success. Key Responsibilities: - Building infrastructure for performance verification and assessing X86 processor performance - Developing targeted tests to evaluate processor performance - Debugging failures in simulation and emulation environments - Writing automatized triages and creating tools using Perl/Ruby or C++ to streamline functional debugging processes - Participating in post-Si bug recreation activities as needed Preferred Experience: - 3-15 years of experience in processor/ASIC performance correlation - Expertise in micro-architecture testing for modern high-performance processors - Proficiency in writing tests and developing infrastructure to test modern processor performance - Skills in programming and scripting languages such as C, C++, Perl, and Python - Strong background in Digital Design, RTL design, model performance improvement, and Processor Architecture - Prior experience in performance correlation of Processor subsystems is advantageous - Comprehensive understanding of computer architecture through relevant research, projects, or industry exposure - Proficiency in programming languages like C/C++ and assembly - Basic knowledge of Verilog Academic Credentials: - Bachelors/Masters in Computer Science, Electrical, or Electronics Engineering with relevant coursework and research projects Join us at AMD, where we are dedicated to transforming lives through technology and creating innovative computing experiences for the future. If you are ready to contribute to our mission and be part of a collaborative and forward-thinking team, we invite you to advance with us.,

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

As an RTL Design Engineer at Google, you will utilize your expertise in designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuit (ASIC). Your role will involve scripting in languages such as Perl or Python, as well as focusing on area, power, and performance optimization. Ideally, you hold a Master's degree or PhD in Electrical Engineering, Computer Science, or possess equivalent practical experience. Experience in designing and developing security blocks or crypto blocks will be beneficial for this position. Join a diverse team at Google that is dedicated to pushing boundaries and creating custom silicon solutions for the future of direct-to-consumer products. Your contributions will drive innovation behind globally loved products, shaping the next generation of hardware experiences with a focus on performance, efficiency, and integration. In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems. This includes tasks such as Micro architecture, RTL coding, UPF definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews, and closure to ensure high-quality and optimized security designs. At Google, our mission is to organize the world's information and make it universally accessible and useful. Our team combines Google AI, Software, and Hardware to create radically helpful experiences, researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power for the betterment of people's lives. Your responsibilities will include participating in test planning and coverage analysis, developing RTL implementations meeting power, performance, and area goals, engaging in synthesis, timing/power closure, FPGA and silicon bring-up, Verilog/SystemVerilog RTL coding, functional and performance simulation debugging, as well as conducting Lint/CDC/FV/UPF checks. Additionally, you will create tools and scripts for task automation and progress tracking.,

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: FPGA Design. Experience:3-5 Years.