914 Rtl Design Jobs - Page 8

You should have a Ph.D. in relevant domains with expertise in Biometric Recognition technologies such as Fingerprint, Iris, and Vein, as well as experience in Augmented Reality (AR) and Virtual Reality (VR). Your background should include knowledge in Multi-view, Stereo, and Depth technologies. Ideally, you hold a degree in EE/Electrical Engineering, with either a BS or MS from a top US school. Your skill set should encompass expertise in Algorithms, Sensor technologies including array sensors, multi sensors, and 2PD sensors. Experience in Vision and Imaging, Computational Photography, and computer vision is essential. You should be well-versed in Image and Video Pipeline, Multimedia Framewo...

As a Silicon Design Engineer at AMD, you will collaborate with formal experts and designers to verify formal properties and drive convergence. You will be responsible for setting up ASIC QA flows for RTL design quality checks, understanding top-level design interfaces, clock structures, and power domains, as well as running various design verification steps like Lint, Synthesis, Static timing analysis, CDC, RDC, DFT, and CLP. Your role will involve coming up with clock constraints, debugging design issues, supporting DFX team for integration tasks, handling multiple PNR blocks, and porting design to different technology libraries. Additionally, you will generate RAMs based on targeted memory...

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in...

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal me...

Wipro Limited (NYSEWIT, BSE507685, NSEWIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. About The Role _x000D_ Role Purpose The purpose of this...

Synopsys (India) Private Limited is looking for ASIC Digital Design, Staff Engineer to join our dynamic team and embark on a rewarding career journey Lead and execute complex engineering projects. Collaborate with cross-functional teams to develop innovative solutions. Mentor and guide junior engineers. Ensure compliance with industry standards and regulations. Conduct technical reviews and assessments. Identify and mitigate project risks. Maintain up-to-date technical documentation.

Synthesis and Timing engineer to participate in the development of large SOCs with multiple physical blocks and 300+ clock domains. He/She must be high energy candidate with strong written and verbal communication skills, technically strong to find solutions and help the team both inside and outside the organization. REQUIRED SKILLS: RTL Design Quality checks, mainly Lint Automation using Python and TCL 5years+ experience, so not an NCG KEY RESPONSIBILITIES: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process...

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL de...

We are seeking a Senior CAD Engineer with 10+ years of experience to join our team in Bangalore. The ideal candidate will be responsible for deploying and supporting front-end tools such as RTL simulators, low power tools, and static RTL checkers. They will also develop scripts to automate regression/debug flows, manage CI/CD processes, interface with EDA vendors, and support global teams across geographies. Proficiency in scripting (Python, Bash, Make, Linux system administration, and version control tools (Git, Mercurial) is essential. Experience in ASIC flows and standard CAD tools is required. Immediate joiners with a notice period of 15 days or less are preferred.

We are seeking a Senior CAD Engineer with 10+ years of experience to join our team in Bangalore. The ideal candidate will be responsible for deploying and supporting front-end tools such as RTL simulators, low power tools, and static RTL checkers. They will also develop scripts to automate regression/debug flows, manage CI/CD processes, interface with EDA vendors, and support global teams across geographies. Proficiency in scripting (Python, Bash, Makefiles), Linux system administration, and version control tools (Git, Mercurial) is essential. Experience in ASIC flows and standard CAD tools is required. Immediate joiners with a notice period of 15 days or less are preferred.

Lead the architecture and RTL design of complex digital blocks and subsystems for ASICs or SoCs Develop RTL using Verilog/SystemVerilog to meet functional and performance specifications Review micro-architecture and provide design solutions optimized for power, performance, and area Work closely with the verification team to ensure thorough test coverage and efficient debugging Collaborate with synthesis, STA, and physical design teams for design closure

This is what you are responsible for Develop verification environments for modules, subsystems, top level and FPGA Build models, checkers and random test frameworks using SystemVerilog and UVM Participate in Low power analysis (UPF), power estimation, C modeling Perform lint, CDC, code coverage, functional coverage Formal verification of modules using SVA assertions Necessary Qualifications Experience in verifying complex subsystems and ASICs Experience with building scalable verification environments from scratch Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc. Exposure to FPGA emulation platforms, silicon bringup, and board debug BTech/MTech in E...

Hiring Freshers Kickstart Your Career in VLSI At PRSsemicon Technologies and Spec2chips semiconductor a PRSgroup of companies, we are shaping the future of semiconductor innovation by building a Global Capability Development Centre. We are looking for fresh graduates passionate about VLSI domains to join our team. Through structured training and hands-on experience, we ensure you gain the technical expertise and industry-relevant skills required to succeed in this dynamic field. Your Journey with Us: Comprehensive Training Gain in-depth knowledge of VLSI design, verification, emulation, DFT, physical design, and analog design based on project needs. Hands-on Experience Work with industry-sta...

As an experienced professional with over 4 years of experience, you will be responsible for developing RTL code for complex digital circuits using Hardware Description Languages (HDLs) like Verilog or VHDL. Your role will involve performing functional verification through simulation and formal methods. Additionally, you will participate in code reviews to ensure compliance with coding standards. In this position, you will analyze timing performance and conduct static timing analysis (STA) to optimize circuit performance. Collaboration with design, verification, and synthesis teams will be essential to ensure successful tape-out of designs. It is crucial to stay informed about the latest RTL ...

As a Senior ASIC RTL Design Engineer at Google, you will play a crucial role in shaping the future of custom silicon solutions that drive Google's direct-to-consumer products. Your expertise in RTL design will be instrumental in delivering innovative hardware experiences with superior performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience, and a minimum of 15 years of experience in ASIC RTL design, you are well-equipped to excel in this role. Your proficiency in Verilog/System Verilog and microarchitecture will be essential in contributing to the development of ARM-based SoCs, interconnects, and...

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance s...

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in ...

We are seeking highy motivated individuas with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to hande the chaenging probems in future technoogies and designs. We are aso ooking for candidates with Strong C/C++background to ead our eading-edge agorithmswithin our EDA soutions to increase our design team’s productivity and chip quaity and performance. Our dynamic goba team is ooking to enist enthusiastic professionas to join word-cass hardware design teams responsibe for deveoping the most chaenging and compex systems in the word. We are seeking energetic, highy motivated individuas wiing to go the extra mie with the aim of heping the overa IBM deveopment team. S...

As a Logic design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers.Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLLAdditiona responsibiities:ogic (RTL) design, timing cosure, CDC anaysis etc.Understand and Design Power efficient ogic.Agie project panning and execution.Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required educ...

Job Description for RTL We are hiring a SoC Integration Engineer with strong expertise in RTL coding and SoC integration flows. The ideal candidate should have hands-on experience with SpyGlass Lint, CDC, DC Synthesis, and VCLSP, along with scripting knowledge. Key Responsibilities: Integrate IP blocks into SoC at RTL level Perform RTL coding and micro-architecture design (Verilog/VHDL) Run and debug SpyGlass Lint, CDC, and DC Synthesis flows Conduct STA and design rule checks Develop automation scripts (Perl, Python, Shell, Tcl) Collaborate with verification and physical design teams Work on VCLSP and SoC-level integration flows Primary Skills: RTL Design: Verilog, VHDL, Micro-architecture ...

Qualcomm India Private Limited is currently seeking experienced Wireless Modem Hardware Model Developers to join their Bangalore Wireless R&D Hardware team. In this role, you will have the opportunity to work on Qualcomms" cutting-edge chipsets in modem WWAN IPs. Your responsibilities will include contributing to the development of flagship modem core IPs covering 5G (NR) and 4G (LTE) technologies. Additionally, you will be part of a team defining and developing next-generation multi-mode 5G modems. Your tasks will involve working on the development and verification of hardware models of modem core IPs, which are developed on the C++/SystemC platform and used as a golden reference for RTL ve...

As a Frontend Principal Engineer specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the front-end stages of integrated circuit development. This role requires a strong technical background in digital design, verification, and project management skills. Additionally, you will oversee product support activities for both the Pre-production and Post-production stages, ensuring the successful initiation, development, and sustainment of semiconductor designs. You should have a minimum of 8+ years of experience in System Architecture for ARM based MCU product development, along with a minimum of 8+ years of experience in RTL Design, Coding, and RTL Integration....

As an RTL Design Engineer, you will be responsible for demonstrating strong design fundamentals with hands-on experience in front-end design flows. Your role will involve designing micro-architecture blocks, RTL coding, and conducting block-level verification. Additionally, you will be expected to perform tasks such as Linting, CDC analysis of reports, and identifying ways to fix violations. You should have hands-on experience in SoC/IP integration and possess an excellent understanding of SoC components such as processors, memories, peripherals, and IOs. It is essential to have a good grasp of at least one protocol like UFS, PCIe, SAS, SATA, or USB. Experience working with ARM or ARC proces...

As a candidate for this role, you should hold a Bachelor's degree in Electrical/Computer Engineering or possess equivalent practical experience. You should also have at least 2 years of experience working with RTL design using Verilog/System Verilog and microarchitecture, particularly in the realm of ARM-based SoCs, interconnects, and ASIC methodology. A Master's degree in Electrical/Computer Engineering would be considered a preferred qualification for this position. Additionally, experience with methodologies for RTL quality checks (such as Lint, CDC, RDC) and low power estimation, timing closure, and synthesis would be beneficial. Join a dynamic team that is dedicated to pushing boundarie...

You Are: An experienced Emulation Engineer with Zebu experience. The Work: Port ASIC and IP RTL code to emulation platforms (Zebu). Build model from released RTL. Generate loadable image(s) for target emulation platform. Run sanity tests to qualify release of the image(s). Release the emulation models to various teams doing functional validation, firmware development and design verification. Assist debug of failures with stakeholder by providing instrumented models and captured waveforms extracted from emulation model. Coordinate with EDA and third-party tools team to validate implementation flows. Heres what you need: A minimum 2 years of experience in Emulation (Zebu) using System Verilog/...