560 Rtl Design Jobs - Page 5

Emulation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: should have emulation experience working on available platforms such as; Palladium, Veloce, or Zebu, as well as experience with compilation, debug, performance, and throughput tuning Experience using Verilog, VHDL design Experience with C/C++ and System Verilog, UVM verification environments Experience writing scripts using Perl, Python, Makefile Debugging experience using tools like waveform, Verdi, Simvision Strong communication skills and ability to work as a team Description You’ll support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches). You’ll be bringing up SOCs on emulation, root causing SoC/Processor test fails and emulator environment issues. – We are in constant collaboration with Design, DV, Power, Silicon Validation, Performance, and Software teams. – Your strong design, debug, communication, and teamwork skills will be essential. – You will also work with leading emulation vendors to debug issues. Skills Experience Zebu Verilog, Python Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USADelaware USATexas

We are seeking a highly skilled and experienced Lead Verification Engineer with expertise in USB/LPDDR and a strong knowledge of Cadence VIP. The ideal candidate will have a deep understanding of low-power design and verification techniques. Responsibilities: Develop and execute comprehensive verification strategies for USB/LPDDR subsystem designs, considering low-power design requirements. Collaborate with cross-functional teams to define verification goals and ensure alignment with project objectives. Design and implement reusable, scalable, and efficient verification testbenches using SystemVerilog/UVM or C based . Leverage Cadence VIP and other verification IPs to accelerate the verification process. Low-Power Design VerificationApply expertise in low-power design and verification techniques to ensure accurate and reliable verification of power management features, including power states, power domains, and power-aware verification methodologies. : Extensive experience (8+ years) in verification. Strong knowledge of Cadence VIP and verification methodologies (SystemVerilog/UVM). Proficiency in low-power design techniques and power-aware verification methodologies. Hands-on experience with industry-standard simulation and verification tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa). Solid understanding of verification languages (SystemVerilog, VHDL) and scripting languages (Perl, Python, TCL). Familiarity with industry standards and protocols related to USB (USB 2.0, USB 3.x) and LPDDR (LPDDR4, LPDDR5). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

We are seeking a skilled and motivated DDR5/SerDes Verification Engineer to join our organization. As a DDR5/SerDes Verification Engineer, you will be responsible for verifying and validating the functionality and performance of DDR5 memory subsystems and high-speed SerDes interfaces. In addition to strong DDR5 and SerDes verification expertise, knowledge and experience with sideband I2C and I3C protocols would be considered a plus. Candidate should have Design and implement advanced verification environments and test benches using SystemVerilog/UVM Experience4-10 Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience Level: 8+ years Location: Bangalore/Hyderabad Skills: Profound expertise in MACSec and Ethernet technologies. MACSec (Media Access Control Security): Proficient in point-to-point security implementation on Ethernet links, adhering to the IEEE 802.1AE-2018 standard. IPsec (Internet Protocol Security): Skilled in establishing security between two devices across an Internet Protocol network. Hands-On Knowledge: Proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), with practical experience in their application. Testbench Development: Demonstrated experience in developing comprehensive Test Benches (TB) and individual verification components. Communication and Leadership: Possesses excellent communication skills and adept at leading and coordinating teams effectively. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Job Location: Bengaluru (BLR) and Hyderabad (HYD) Experience: 7 to 20 years : We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of ARM Micro Architecture to join our team. In this role, you will play a key role in the development of complex digital designs and contribute to the success of our cutting-edge projects. The ideal candidate will have a proven track record in RTL design and a deep understanding of ARM Micro Architecture. Key Responsibilities: Collaborate with cross-functional teams to define and develop RTL designs for advanced microprocessor-based projects. Design, implement, and verify digital logic blocks and modules in accordance with project specifications and quality standards. Utilize your expertise in ARM Micro Architecture to optimize and enhance design efficiency. Perform RTL simulations and conduct thorough functional and timing analysis. Identify and resolve design issues, ensuring the delivery of high-quality RTL designs. Stay up-to-date with industry trends and emerging technologies to continually improve design methodologies. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience as an RTL Design Engineer with 7 to 20 years of relevant work experience. Strong knowledge of ARM Micro Architecture and its application in RTL design. Proficiency in RTL design tools and methodologies. Experience with simulation and verification tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS). Excellent problem-solving skills and attention to detail. Effective communication and collaboration skills. Ability to work effectively in a dynamic and fast-paced environment. If you are a highly motivated and experienced RTL Design Engineer with a passion for innovation and a strong background in ARM Micro Architecture, we encourage you to apply for this exciting opportunity. Join our team and contribute to the development of cutting-edge technology solutions. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification and possess a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). This role specifically requires expertise in GLS (Gate-Level Simulation). Key Responsibilities: IP and SOC Verification Conduct IP and SOC verification activities to ensure the functionality and correctness of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate strong knowledge of SystemVerilog and Universal Verification Methodology for efficient and effective verification processes. Gate-Level Simulation (GLS) Proficiency in Gate-Level Simulation is a mandatory requirement for this position. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM). Proficiency in Gate-Level Simulation (GLS). If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of integrated circuits, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly experienced Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong foundation in SystemVerilog (SV) and Universal Verification Methodology (UVM). In addition to standard verification skills, this role requires expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST (Memory Built-In Self-Test), SCAN, PG (Pattern Generator), and PM (Pattern Memory). Key Responsibilities: IP and SOC Verification Perform comprehensive IP and SOC verification to ensure the reliability and functionality of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate a strong understanding of SystemVerilog and Universal Verification Methodology for efficient verification processes. CDP, GDP, DFT DV Expertise Possess expertise in Compressed Data Pattern (CDP) and Generic Data Pattern (GDP) methodologies. Proficiency in Design for Test in Design Verification (DFT DV) techniques, including JTAG, MBIST, SCAN, PG, and PM. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong knowledge of SystemVerilog (SV) and Universal Verification Methodology (UVM). Expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST, SCAN, PG, and PM. If you are a talented Design Verification Engineer with a deep understanding of IP and SOC verification, as well as specialized expertise in CDP, GDP, and DFT DV methodologies, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Number of Open Positions: 7 Location: Bangalore Experience: 4 to 7+ years : We are currently seeking talented and experienced Design Verification Engineers to join our team in Bangalore. As a Design Verification Engineer, you will be responsible for ensuring the functionality, performance, and reliability of our complex designs, with a focus on Core Data Path (CDP), Graphics Data Path (GDP), USB4 (USB 4.0), Power Gating (PG), and Power Management (PM) domains. We are looking for candidates with 4 to 7+ years of relevant experience in design verification. Key Responsibilities: Verification Planning: Collaborate with design and architecture teams to develop comprehensive verification plans for CDP, GDP, USB4, PG, and PM components. Testbench Development: Create and maintain advanced testbenches, including constrained-random and assertion-based methodologies, to thoroughly verify design functionality. Functional and Coverage Testing: Execute functional tests and track coverage metrics to ensure exhaustive testing of design features. Protocol Verification: Verify compliance with industry-standard protocols, including USB4, and identify and address protocol violations. Bug Reporting and Debugging: Document and report issues, and work closely with design teams to resolve bugs in a timely manner. Performance Verification: Assess and verify the performance of data path components, ensuring they meet specified requirements. Power Verification: Verify power management and power gating strategies to optimize power consumption. Scripting and Automation: Develop and use scripting languages and automation tools to streamline verification processes. Documentation: Prepare detailed verification plans, test reports, and documentation. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. 4 to 7+ years of experience in design verification. Strong knowledge of CDP, GDP, USB4, PG, and PM domains. Experience with industry-standard verification methodologies and tools. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. If you are a highly motivated and detail-oriented Design Verification Engineer with a passion for ensuring the quality and reliability of complex designs, we encourage you to apply. Join our team to work on cutting-edge technologies and contribute to the success of our projects. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Redefine how verification is done!Were hiring Functional Verification Engineers for Bangalore to tackle IP/SoC verification, cache coherency, and more.Experience Required4"“18 YearsKey Skills: High-speed protocols, low-power simulations (UPF), System Verilog/UVMBe a part of the innovation journey! Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Job Title: ASIC RTL Design Engineer Position Experience Level: 6 to 10 years Location: Bangalore : We are seeking a highly skilled and experienced ASIC RTL Design Engineer to join our team in Bangalore. The successful candidate will have 6 to 10 years of relevant experience and will play a crucial role in the design and integration of RTL components for complex ASIC projects. The candidate should possess a strong background in RTL UPF, SoC Design Integration, and multi-domain UPF methodologies. Additionally, a strong understanding of resolving VSI issues is required to excel in this role. Key Responsibilities: RTL UPF Experience: The ideal candidate should have a proven track record of working with RTL UPF (Unified Power Format) to efficiently manage power intent for ASIC designs. SoC Design Integration: Experience in the integration of RTL components into System-on-Chip (SoC) designs, ensuring seamless functionality and performance. Multi-Domain UPF: Proficiency in working with multi-domain UPF to address power management across different aspects of the design. VSI Issue Resolution: Ability to identify and rectify VSI (Voltage Storm Immunity) issues to enhance the reliability and robustness of the ASIC design. Additional : In addition to the core responsibilities, candidates who have experience in addressing UPF constraints and issues during the synthesis process and Engineering Change Orders (ECOs), including mitigating RTL-UPF mismatches, will be considered favorably. This position offers an exciting opportunity to work on cutting-edge ASIC projects, pushing the boundaries of design and innovation. If you are a seasoned RTL Design Engineer with the requisite experience and skills, we encourage you to apply and join our dynamic team in Bangalore. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Take the lead in advanced design verification!Were looking for a Senior Design Verification Engineer in Bangalore to work onHBM, DDR, UCIe, PCIe protocols, and more.Key Skills: System Verilog/UVM, protocol verificationExperience Required3+ YearsJoin our team and help shape groundbreaking designs. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Strong communication skills, both written and verbal Experience: At least 8 years of professional experience in the field Skills: Proficiency in Trace, Cross-Trigger, JTAG, and AXI protocols Expertise in security protocols, real boot processes, Debug mode, Warm reset, power management, and LP-UPF Previous experience with AMD is considered an advantage NoteInterested candidates should submit a detailed resume highlighting their relevant experience and skills. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: Minimum 8 years of experience in functional Design Verification (DV) Proficiency in low-power UPF-based verification Strong debugging skills Skills: In-depth understanding of power gating and power management techniques Familiarity with AXI and SMN protocols Previous experience with AMD is advantageous Location: Hiring for Bangalore (BLR) or Hyderabad (HYD) locations NotePlease provide a detailed resume highlighting relevant experience and skills. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Let your ideas power the next wave of technology!Were hiring Design Verification Engineers for Bangalore and Hyderabad.Experience Required4"“18 YearsKey Skills: HSIO protocols like PCIe, DDR5, HBM, USB, low-power simulationsWork on cutting-edge verification projects and take your career to new heights. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: 5-8 years of experience in RTL Design with exposure to synthesis OR 8+ years of experience in RTL Design Strong understanding of digital basics Proficiency in RTL coding (Verilog), IP design, and RTL integration Hands-on experience with LINT, CDC, and RDC Experience in writing UPFs and CLP/VCLP checks Familiarity with synthesis flow and validating design constraints Specific domain knowledge in ARM protocols, PCIe, Ethernet, RISC V, DDR, etc. Strong scripting knowledge Responsibilities: Understand the overall ASIC flow and effectively collaborate with multiple teams such as DV, DFT, Synthesis/Implementation, and PD teams Ability to take on the role of a Technical Manager while maintaining hands-on contributions NoteInterested candidates should provide a detailed resume highlighting relevant experience and skills. Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaHyderabad

Calling all innovators and creators!Were hiring RTL Design Engineers for Bangalore to work on complex ASICdesigns and integrations.Experience Required3"“25 YearsKey Skills: RTL design, low-power methodologies, scripting (Perl, Python, TCL)Join us and design the future of technology! Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

You are invited to join Qualcomm India Private Limited as an IP Design Engineer within the Engineering Group > Systems Engineering team. As a highly skilled professional with a background in microarchitecture design and RTL design for complex IPs, you will play a key role in the development of innovative IP solutions, ensuring high-quality and reliable designs. Your main responsibilities will include leading the design and development of IP solutions from scratch, collaborating with cross-functional teams to define design specifications, ensuring design quality and performance through PLDRC and synthesis processes, maintaining detailed documentation, troubleshooting complex design issues, and staying up-to-date with industry trends and best practices. To excel in this role, you should possess 7-10 years of experience in IP design, with a focus on microarchitecture and RTL design, extensive hands-on experience with AMBA or PCIe protocols, proficiency in PLDRC and synthesis tools, a strong understanding of digital design principles, experience with design verification and validation, excellent problem-solving skills, and the ability to work independently and in a team environment. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is required. Preferred skills include experience with industry standard design flow tools, knowledge of ASIC design flows, familiarity with scripting languages like Python for automation, and experience with version control systems like Git and clearcase. Qualcomm is an equal opportunity employer committed to providing accommodations for individuals with disabilities during the application/hiring process. If you require an accommodation, please contact disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures to protect confidential and proprietary information. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through this site. Unsolicited submissions will not be accepted. For more information about this role, please contact Qualcomm Careers.,

Role : ASIC RTL Engineer / Digital Design Location . pan India or Onsite. SoC subsystem/IP design, RTL quality checks (Lint, CDC) If you interested so please share your updated cv at sugrabano@praxists.co.in - 9582126775

As a successful candidate for this role, you should possess a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or have equivalent practical experience. You should have at least 10 years of experience in Camera ISP image processing or other multimedia IPs like Display or Video Codec. Additionally, you should have a solid background with System Verilog Assertions (SVA), assertion-based verification, and formal verification, with at least 4 years of experience in people management and employee development. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, focusing on computer architecture. It would be advantageous to have experience in low-power design verification, working with RTL design and integration teams to enhance team productivity and velocity, and collaborating with software teams to define hardware/software interfacing. Join our team that is dedicated to pushing boundaries and creating custom silicon solutions to drive Google's direct-to-consumer products into the future. You will play a crucial role in innovating products that are beloved by people worldwide, shaping the next generation of hardware experiences with superior performance, efficiency, and integration. As part of our mission to organize the world's information and make it universally accessible and useful, we combine the expertise of Google AI, Software, and Hardware to develop groundbreaking technologies. Our goal is to make computing faster, seamless, and more powerful, ultimately enhancing people's lives through technology. In this role, your responsibilities will include leading a team of individuals, setting and communicating individual and team priorities aligned with organizational goals, providing regular performance feedback and coaching, collaborating cross-functionally to debug failures and ensure design functional correctness, devising test plans and verification strategies, planning the verification of complex Camera ISP hardware IPs, and creating advanced verification environments using System Verilog and UVM. If you are passionate about driving innovation, working on cutting-edge technologies, and contributing to the advancement of hardware experiences, we invite you to join us on this exciting journey.,

You should be an ASIC designer with a minimum of 1-15 years of experience in RTL design using Verilog/System Verilog. Your expertise should cover all aspects of the RTL design flow, including Specification/Microarchitecture definition, design and verification, Timing Analysis, DFT, and Implementation. You should also have experience in Integration, RTL signoff tools, UPF/Low power signoff, CDC/RDC, and Lint. Your domain knowledge should be strong in Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures. As a highly motivated individual, you should be a self-starter with excellent interpersonal skills and the ability to work effectively in a team. Strong communication, critical thinking, and problem-solving skills are essential for this role. Preferred education for this position is any degree.,

As a Senior ASIC RTL Design Engineer at Google, you will be a key member of a team dedicated to creating custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions globally. Your expertise will play a crucial part in shaping the future of hardware experiences, ensuring unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. As part of the Devices & Services team, you will have the opportunity to combine the best of Google AI, Software, and Hardware to create innovative and helpful user experiences. You will be involved in researching, designing, and developing new technologies and hardware to enhance user interactions with computing, making them faster, seamless, and more powerful. **Responsibilities:** - Lead a team to deliver fabric interconnect design for ASICs. - Develop and enhance RTL design to meet power, performance, area, and timing objectives. - Define key details such as interface protocols, block diagrams, data flow, and pipelines. - Oversee RTL development and debug functional/performance simulations. - Collaborate effectively with multi-disciplined and multi-site teams. **Minimum Qualifications:** - Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. - 15 years of experience in ASIC RTL design. - Proficiency in RTL design using Verilog/System Verilog and microarchitecture. - Experience with ARM-based SoCs, interconnects, and ASIC methodology. **Preferred Qualifications:** - Master's degree in Electrical Engineering or Computer Engineering. - Proven experience in driving multi-generational roadmap for IP development. - Experience in leading interconnect IP design teams for low power SoCs.,

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: FPGA Design.: Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT.: Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT Experience : 1-3 Years.

Job Description In your new role you will: Create and define verification plans for SOC integration verification; Develop verification environments for our ICs using UniversalVerification Methodology (UVM ). Develop test scenarios using SystemVerilog and SW based C/CPP tests . Utilise Perspec/PSS portable stimulus tooling to enable randomised SW based tests. Develop assertions in SystemVerilog for formal verification; Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies; Work closely with IP verification teams to align work split and information sharing. Your Profile You are best equipped for this task if you have: You have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline; You have at least two years of experience in Constrained-Random Metric-Driven Verification or SOC integration verification. You have capabilities and experience in working with microcontroller-based ICs, as well as security and safety requirements; You have good know-how with UVM especially using SystemVerilog. You have some knowledge of SW-based testing (writing/executing SW on embedded CPUs) Have knowledge of RTL design (System Verilog); Ideally have knowledge of working with Verification IPs (VIPs) Contact: Gowri Shenoy, LinkedIn We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.