Physical Design Engineer (VLSI)

5 years

15 - 35 Lacs

Posted:2 days ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

Job Description: Physical Design (PD) Engineer – VLSI

Experience:

5+ Years

Location:

Bangalore (Only local candidates)

Notice Period:

Immediate to Short Notice OnlyRole OverviewWe are seeking an experienced

Physical Design (PD) Engineer

with strong hands-on expertise across the complete PD flow. The ideal candidate should be capable of independently planning and executing all aspects of physical design for complex VLSI/SoC designs, with mandatory experience on the

Innovus tool

.Key Responsibilities
  • Independently plan and execute end-to-end Physical Design activities from netlist to GDSII.
  • Perform floorplanning, placement, optimization, and place & route using Innovus.
  • Handle Clock Tree Synthesis (CTS), clock distribution, and timing optimization.
  • Achieve timing convergence including setup, hold, and OCV/CRPR scenarios.
  • Perform RC extraction and close timing post-extraction.
  • Conduct IR drop and EM analysis, and address power integrity issues.
  • Ensure clean signoff closure including DRC/LVS and physical verification.
  • Work on Power, Signal Integrity analysis, and DFM checks.
  • Collaborate closely with STA, DFT, and design teams to resolve PD-related issues.

Required Skills & Qualifications

  • 5+ years of hands-on experience in Physical Design (VLSI).
  • Deep understanding of synthesis, P&R, CTS, timing closure, and signoff methodologies.
  • Strong experience with Cadence Innovus (mandatory).
  • Solid knowledge of IR/EM analysis, DRC/LVS closure, and physical verification flows.
  • Experience handling complex SoC designs at advanced technology nodes is a plus.
Location & Availability
  • Location: Bangalore only
  • Joining: Immediate to short notice candidates preferred
Skills: synthesis,cts,innovus,physical design,timing,route

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