Lead / Senior DFT Engineer

About the Role

Sun Silicon Solutions Pvt Ltd is a fast-growing semiconductor company developing advanced ASIC and SoC solutions. We are seeking a highly experienced DFT Engineer who will define, own, and drive DFT architecture and sign-off for complex IPs and full-chip SoCs.

This role is meant for engineers who have taken multiple designs to silicon, can independently handle DFT closure, and act as a technical mentor and decision-maker within the DFT organization.

You will collaborate closely with Design, Verification, Physical Design, STA, and Post-Silicon/Test teams, covering the complete journey from RTL to production silicon.

Key Responsibilities

DFT Architecture & Ownership

Define end-to-end DFT strategy for complex IPs and SoCs

Own scan architecture design (full scan, partial scan, hierarchical scan)

Architect and integrate:

o Scan chains, compression logic, test controllers

o Test access mechanisms (TAM), IJTAG where applicable

Drive SoC-level DFT integration and sign-off

ATPG, Coverage & Sign-off

Own ATPG generation and closure for:

o Stuck-at, transition, path-delay, and at-speed faults

Analyze and improve test coverage, pattern count, and test time

Lead DFT DRC/Lint closure and resolve complex violations

Sign off DFT readiness for tape-out

Memory & Logic BIST

Define and integrate MBIST/LBIST architectures

Drive MBIST/LBIST pattern generation, simulation, and coverage closure

Work closely with memory vendors and PD teams on BIST-related issues

Cross-Team Collaboration

Partner with RTL and PD teams to resolve:

o Scan/timing interactions

o Clocking, reset, and low-power DFT challenges

Work with STA teams on at-speed and test-mode timing closure

Collaborate with Test Engineering and Foundry teams for ATE readiness

Silicon Bring-up & Yield

Lead post-silicon debug, silicon bring-up, and failure analysis

Analyze production test results and drive yield improvement initiatives

Support test program development and volume ramp

Technical Leadership

Mentor and review work of junior and mid-level DFT engineers

Establish DFT best practices, checklists, and reusable methodologies

Drive continuous improvement in DFT flows and automation

Required Skills

Must-Have Technical Skills

810 years of hands-on experience in DFT for ASIC/SoC

Deep expertise in:

o Scan architecture and compression techniques

o ATPG fault models (stuck-at, transition, path-delay)

o SoC-level DFT integration and sign-off

Strong understanding of:

o Clocking, resets, CDC, and low-power DFT

o Test-mode timing and STA interactions

Proven experience with multiple successful tape-outs

Tools & Technologies

Strong hands-on experience with:

o Synopsys DFT Compiler / TestMAX

o Siemens Tessent (Scan, ATPG, MBIST, LBIST)

• Expertise in JTAG / IEEE 1149.1 / IJTAG (1687)
• Experience with low-power DFT (UPF-aware flows)
• Programming & Automation
• Strong scripting skills in Tcl, Python, and/or Shell
• Ability to build automation for coverage analysis, DRC closure, and reporting

What We Look For

• Strong technical ownership and accountability
• Ability to independently drive DFT decisions and trade-offs
• Excellent debugging and analytical skills
• Clear communication with cross-functional teams
• Experience thriving in fast-paced startup environments

Education

• B.E./B.Tech or M.E./M.Tech in
• Electronics / Electrical / VLSI / Embedded Systems / Related fields