Senior / Lead RTL Design Engineer

About the Role

We are a fast-growing semiconductor startup building next-generation ASIC and SoC

products. We are looking for a Senior / Lead RTL Design Engineer who will own critical RTL blocks and subsystems from specification through silicon and play a key role in architecture definition, integration, and design quality.

This role is intended for engineers who have taken multiple designs to tape-out, can

independently drive micro-architecture and RTL closure, and act as a technical leader and

mentor while collaborating closely with architecture, verification, physical design, DFT, and firmware teams.

Key Responsibilities

RTL Architecture & Design Ownership

Own end-to-end RTL development for complex blocks/subsystems from microarchitecture

to tape-out

Translate system and architecture specifications into efficient, scalable RTL

Define interfaces, pipelines, clocking, reset strategies, and configuration schemes

Review and approve RTL developed by junior engineers

Implementation & Debug

Design and maintain high-quality synthesizable RTL using Verilog/SystemVerilog

Drive functional debug using simulation, assertions, and waveform analysis

Ensure RTL meets performance, power, and area (PPA) goals

Proactively identify and resolve corner cases and system-level issues

Design Quality & Sign-off

Own and close lint, CDC, RDC, and low-power checks

Support synthesis, timing analysis, and ECO closure

Collaborate with PD and STA teams on timing intent and RTL optimizations

Ensure RTL readiness for tape-out

Cross-Functional Collaboration

Work closely with verification teams to ensure full functional coverage

Support SoC integration, IP bring-up, and top-level debug

Collaborate with DFT teams on scan, MBIST, and test-mode requirements

Interface with firmware/software teams on register maps and HWSW interaction

Technical Leadership

Mentor junior and mid-level RTL engineers

Participate actively in architecture and design reviews

Establish RTL coding guidelines, best practices, and checklists

Drive continuous improvement in design quality and reuse

Required Skills

Must-Have Technical Skills

8-10 years of hands-on experience in RTL design for ASIC/SoC

Strong expertise in:

o Digital design fundamentals (FSMs, pipelining, clock/reset design)

o Micro-architecture definition and block-level ownership

o Verilog / SystemVerilog (synthesizable RTL)

Solid understanding of:

o ASIC design flow from RTL to GDS

o Synthesis and timing concepts

o Power-aware RTL design and clock gating

Experience with multiple successful tape-outs

Strong debugging and analytical skills

Comfortable working in Linux-based environments

Good to Have

• Experience with SoC-level architecture and integration
• Strong knowledge of AMBA protocols (AXI, AHB, APB)
• Working understanding of UVM-based verification
• Exposure to DFT concepts (scan, MBIST, LBIST)
• Experience with low-power design techniques and UPF-aware RTL
• Scripting skills (Python / Tcl / Shell)
• Experience supporting post-silicon debug or silicon bring-up

What We Look For

• Strong ownership mindset accountable for design quality and outcomes
• Ability to independently drive complex RTL blocks to closure
• System-level thinking beyond individual modules
• Clear technical communication and collaboration skills
• Comfort working in a fast-paced, startup environment

Education

• B.E./B.Tech or M.E./M.Tech in
• Electronics / Electrical / VLSI / Embedded Systems / Related fields