Lead Design Verification-IP/SoC

Role Overview

Lead Design Verification Engineer

Key Responsibilities

• Define and drive the verification plan based on design specifications and functional requirements.
  
• Architect and develop reusable UVM/SystemVerilog-based testbenches.
  
• Own IP/SoC-level functional verification from test planning to coverage closure.
  
• Work closely with RTL, DFT, and firmware teams for seamless integration and debug.
  
• Guide and mentor junior engineers; conduct reviews and knowledge sessions.
  
• Contribute to verification methodology improvements and best practices.
  
• Perform regression setup, coverage analysis, and issue tracking.
  
• Deliver high-quality, first-time-right silicon.
  

Required Skills

• Strong experience in IP/SoC verification using

  SystemVerilog/UVM

  .
• Solid understanding of verification methodologies and simulation flows.
  
• Hands-on with tools like VCS, Questa, Verdi, SimVision, etc.
  
• Experience with standard bus protocols like AXI, AHB, PCIe, USB, etc.
  
• Good debugging skills using waveform viewers and log analysis.
  
• Experience in writing assertions and functional coverage models.
  
• Knowledge of scripting (Python, Perl, TCL) is a plus.
  
• Strong communication and leadership abilities.
  

Preferred Qualifications

• Experience with formal verification, assertion-based verification (SVA).
  
• Exposure to low-power verification and UPF flows.
  
• Familiarity with safety/security standards (e.g., ISO 26262, DO-254).
  
• Experience working with emulation platforms and FPGA prototyping.

Location: