Job Title: Physical Design Engineer PnR / STA Location: Bangalore Experience: 6 - 10 Years Notice Period: 015 Days (Immediate joiners preferred) Job Type: Full-Time | Onsite Job Description: We are looking for a skilled Physical Design Engineer with strong experience in Place & Route (PnR) and Static Timing Analysis (STA) to join our growing silicon engineering team. The ideal candidate will take ownership of block-level or full-chip implementation and timing closure for high-performance, low-power SoCs. Key Responsibilities: Drive RTL to GDSII flow for block-level or full-chip implementation Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (LVS/DRC) Execute timing closure using PrimeTime (STA) and handle multi-mode, multi-corner (MMMC) analysis Develop and optimize power, performance, and area (PPA) Collaborate closely with RTL, DV, DFT, and backend teams to resolve implementation and timing issues Work on advanced node technologies (7nm/5nm/3nm) with signoff-quality methodologies Create scripts for flow automation and report generation Required Skills: Hands-on experience with industry-standard tools (Innovus, ICC2/Fusion Compiler, PrimeTime, RedHawk/Voltus) Strong knowledge of PnR flow , STA , RC extraction , and signal/power integrity Solid understanding of timing constraints (SDC) and timing exceptions Familiarity with low-power design techniques, multi-voltage domains, and UPF Experience with scripting languages: Tcl , Perl , Python Strong problem-solving skills and ability to work in a fast-paced team environment Preferred Qualifications: Bachelor’s/Master’s degree in Electronics, Electrical, or VLSI Engineering Tapeout experience on multiple SoC designs Exposure to hierarchical and flat design methodologies Why Join Us? Work on high-volume SoCs with leading semiconductor teams Exposure to cutting-edge EDA tools and latest technology nodes Transparent career growth path and technical mentorship Competitive compensation and work-life balance.

Position: Lead RTL Design Engineer (ASIC/FPGA) Location: Bangalore Experience: 7+ years Senior / Lead Level Role Overview Were seeking a proactive Lead RTL Engineer to define micro-architectures, implement robust RTL, guide integration, and collaborate across ASIC and FPGA domains. You will architect complex subsystems and mentor a high-performing team. Key Responsibilities Micro-architecture & Specifications: Create block-level design docs & detailed RTL micro-architecture for highcomplexity IP/subsystems. RTL Coding & Review: Develop clean, synthesizable RTL in Verilog/SystemVerilog/VHDL. Ensure code quality via lint/CDCC/static timing checks. Integration & IP Subsystems: Integrate with SoC/FPGA subsystems—protocols like AMBA/AXI, interconnects, memory, serial interfaces. Synthesis & Timing Closure: Lead flows using Design Compiler, Primetime, STA tools to meet timing and area goals. Verification & Debug: Coordinate with verification leads, support testbench development, and debug RTL—functional, wavebased, simulation. Leadership & Mentorship: Mentor engineers, lead reviews, steer integration, and liaise across RTL, verification, physical design, and architecture teams. Toolchain & Scripting: Script for automation (Tcl, Python, Perl, Shell); manage version control (e.g. Perforce, Git) . Innovation & Best Practices: Drive RTL design best practices, stay current with EDA tools, lowpower (UPF), CDC, linting, and continuous improvement. Required Qualifications Bachelor’s/Master’s in EE/CE or similar. 7+ years in RTL for ASIC/FPGA, +3 years in a leadership role. Expert in Verilog/SystemVerilog/VHDL, microarchitecture, FSMs, datapaths, CDC. Experienced with SoC/IP integration—AXI, AHB, APB, PCIe, USB, Ethernet, DDR, etc. Proficient with synthesis, STA, CDC, lint tools, DFT flows. Solid scripting with Tcl/Python/Perl/Shell and version control systems. Strong communication, documentation, team leadership, and cross-team collaboration skills. Preferred Skills FPGA prototyping and hardware bring-up expertise. Low-power methodologies (UPF, power gating). ASIC methodology experience (synthesis, timing, DFT, PPA closure). Familiarity with UVM verification, formal methods. Integration experience with high-speed or accelerator IP (NoC, memory controllers, etc.). What You’ll Get High-impact leadership in advanced RTL design for ASIC/FPGA cutting-edge chips. Opportunity to mentor and build a top-tier RTL team. Collaborative culture working with architecture, verification, PD, and system teams. Learning, ownership, and visibility across end-to-end chip delivery.

Job Title : DFT Engineer Location : Bangalore, India Experience : 4 to 8 Years Role Overview We are looking for a passionate and detail-oriented Design-for-Test (DFT) Engineer to join our dynamic ASIC design team. As a DFT Engineer, you will be responsible for architecting and implementing robust test strategies to ensure first-pass silicon success in complex SoC designs. Key Responsibilities Develop and implement DFT architecture and methodologies for SoC/ASIC designs Design and insertion of scan chains , MBIST , LBIST , and boundary scan (JTAG) Work closely with RTL, STA, and Physical Design teams to integrate and validate DFT logic Generate and validate test patterns (ATPG/MBIST) and support silicon bring-up and validation Ensure DFT logic meets coverage goals , timing, and area/power constraints Work with ATE teams on test vectors and debug silicon issues Required Skills & Qualifications 4-8 years of experience in DFT implementation and verification Hands-on experience with tools like Mentor Tessent, Synopsys DFT Compiler, TestMax, TetraMAX Strong knowledge of scan insertion , ATPG , JTAG (IEEE 1149.x) , MBIST , and LBIST Good understanding of ASIC/SoC design flow , RTL to GDSII Proficiency in scripting (TCL, Perl, or Python) for automation Experience working with advanced technology nodes (16nm, 7nm or below) is a plus Excellent analytical, problem-solving, and communication skills Nice to Have Experience in DFT signoff and silicon debug Knowledge of safety-critical designs (ISO 26262) or low-power DFT techniques Familiarity with ATE patterns and post-silicon validation Why Join Us? Work on industry-leading SoCs and IPs Collaborate with some of the best minds in the semiconductor industry Fast-paced, innovation-driven, and engineer-friendly environment Flexible work culture and competitive benefits

Role Overview As a Lead Design Verification Engineer , you will own verification strategy and execution for high-complexity IP and SoC designs. You will be responsible for planning, leading teams, defining testbench architecture, and ensuring coverage-driven closure. Key Responsibilities Define and drive the verification plan based on design specifications and functional requirements. Architect and develop reusable UVM/SystemVerilog-based testbenches. Own IP/SoC-level functional verification from test planning to coverage closure. Work closely with RTL, DFT, and firmware teams for seamless integration and debug. Guide and mentor junior engineers; conduct reviews and knowledge sessions. Contribute to verification methodology improvements and best practices. Perform regression setup, coverage analysis, and issue tracking. Deliver high-quality, first-time-right silicon. Required Skills Strong experience in IP/SoC verification using SystemVerilog/UVM . Solid understanding of verification methodologies and simulation flows. Hands-on with tools like VCS, Questa, Verdi, SimVision, etc. Experience with standard bus protocols like AXI, AHB, PCIe, USB, etc. Good debugging skills using waveform viewers and log analysis. Experience in writing assertions and functional coverage models. Knowledge of scripting (Python, Perl, TCL) is a plus. Strong communication and leadership abilities. Preferred Qualifications Experience with formal verification, assertion-based verification (SVA). Exposure to low-power verification and UPF flows. Familiarity with safety/security standards (e.g., ISO 26262, DO-254). Experience working with emulation platforms and FPGA prototyping. Location: Bangalore / Hyderabad / Pune Experience: 815 Years Notice Period: Immediate to 30 Days Company: ADV Logics – Empowering Next-Gen VLSI Innovation