DFT Engineer-II/Senior

Advlogics

4 - 8 years

12 - 22 Lacs

Bengaluru

Posted:1 month ago| Platform:

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Skills Required

Scan Insertion DFT Atpg Design Flow RTL Insertions Bist Boundary Scan Perl TCL Mbist Scripting Python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Job Title

Location

Role Overview

Design-for-Test (DFT) Engineer

Key Responsibilities

Develop and implement
DFT architecture and methodologies
for SoC/ASIC designs
Design and insertion of
scan chains
,
MBIST
,
LBIST
, and
boundary scan (JTAG)
Work closely with RTL, STA, and Physical Design teams to integrate and validate DFT logic
Generate and validate
test patterns
(ATPG/MBIST) and support silicon bring-up and validation
Ensure DFT logic meets
coverage goals
, timing, and area/power constraints
Work with ATE teams on test vectors and debug silicon issues

Required Skills & Qualifications

4-8 years of experience in
DFT implementation and verification
Hands-on experience with tools like
Mentor Tessent, Synopsys DFT Compiler, TestMax, TetraMAX
Strong knowledge of
scan insertion
,
ATPG
,
JTAG (IEEE 1149.x)
,
MBIST
, and
LBIST
Good understanding of
ASIC/SoC design flow
, RTL to GDSII
Proficiency in scripting (TCL, Perl, or Python) for automation
Experience working with
advanced technology nodes (16nm, 7nm or below)
is a plus
Excellent analytical, problem-solving, and communication skills

Nice to Have

Experience in
DFT signoff and silicon debug
Knowledge of safety-critical designs (ISO 26262) or low-power DFT techniques
Familiarity with ATE patterns and post-silicon validation

Why Join Us?

Work on
industry-leading SoCs and IPs
Collaborate with some of the
best minds in the semiconductor industry
Fast-paced, innovation-driven, and engineer-friendly environment
Flexible work culture and competitive benefits

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