Posted:6 days ago|
Platform:
Work from Office
Full Time
Job Title: Physical Design Engineer PnR / STA Location: Bangalore Experience: 6 - 10 Years Notice Period: 015 Days (Immediate joiners preferred) Job Type: Full-Time | Onsite Job Description: We are looking for a skilled Physical Design Engineer with strong experience in Place & Route (PnR) and Static Timing Analysis (STA) to join our growing silicon engineering team. The ideal candidate will take ownership of block-level or full-chip implementation and timing closure for high-performance, low-power SoCs. Key Responsibilities: Drive RTL to GDSII flow for block-level or full-chip implementation Perform floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (LVS/DRC) Execute timing closure using PrimeTime (STA) and handle multi-mode, multi-corner (MMMC) analysis Develop and optimize power, performance, and area (PPA) Collaborate closely with RTL, DV, DFT, and backend teams to resolve implementation and timing issues Work on advanced node technologies (7nm/5nm/3nm) with signoff-quality methodologies Create scripts for flow automation and report generation Required Skills: Hands-on experience with industry-standard tools (Innovus, ICC2/Fusion Compiler, PrimeTime, RedHawk/Voltus) Strong knowledge of PnR flow , STA , RC extraction , and signal/power integrity Solid understanding of timing constraints (SDC) and timing exceptions Familiarity with low-power design techniques, multi-voltage domains, and UPF Experience with scripting languages: Tcl , Perl , Python Strong problem-solving skills and ability to work in a fast-paced team environment Preferred Qualifications: Bachelor’s/Master’s degree in Electronics, Electrical, or VLSI Engineering Tapeout experience on multiple SoC designs Exposure to hierarchical and flat design methodologies Why Join Us? Work on high-volume SoCs with leading semiconductor teams Exposure to cutting-edge EDA tools and latest technology nodes Transparent career growth path and technical mentorship Competitive compensation and work-life balance.
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