Digital Design Verification Engineer (3 To 5 Years) Immediate Joiner

Key Responsibilities

• Perform IP-level and SoC-level functional verification using

  SystemVerilog

  and

  UVM

  methodologies.
• Develop, enhance, and maintain

  UVM-based testbenches

  , sequences, monitors, scoreboards, and coverage models.
• Understand

  RTL (Verilog)

  to support debugging and verification closure.
• Create and execute

  test plans

  , functional coverage, and assertion-based verification.
• Work on high-speed peripherals such as

  USB 2.0 / USB 3.0

  and

  PCI Express (PCIe)

  .
• Verify CPU subsystems with knowledge of

  ARM

  and

  DSP

  architectures.
• Perform verification for

  AXI/AHB

  bus interfaces, memory subsystems, and multimedia/audio subsystems.
• Handle

  power-aware verification

  , including low-power modes, UPF-based simulation, isolation/retention logic checks.
• Perform

  Gate-Level Simulation (GLS)

  with SDF annotation and debug timing-related issues.
• Generate

  test vectors

  for various verification scenarios and coverage goals.
• Work with version control tools such as

  ClearCase

  or

  Perforce

  .
• Use scripting languages (

  Perl, Tcl, Python

  ) for automation, regression setup, log parsing, and flow enhancement.
• Collaborate with design, architecture, and validation teams to ensure full verification closure.
  

Required Skills:

Technical Skills

• Strong knowledge of

  Digital Design

  , IP verification, and SoC-level integration.
• Expertise in

  SystemVerilog

  and

  UVM

  ; familiarity with

  SystemC

  is a plus.
• Good understanding of

  Verilog RTL

  .
• Knowledge of

  ARM/DSP

  CPU architecture.
• Hands-on experience with

  USB 2.0/3.0

  ,

  PCIe

  , and other high-speed protocols.
• Familiarity with

  AXI/AHB

  bus protocols.
• Experience in

  memory subsystem verification

  (SRAM/DRAM/cache).
• Exposure to

  audio/multimedia verification

  is a plus.
• Strong understanding of

  power-aware verification

  concepts.
• Experience with

  GLS, SDF

  , and timing debug.

Tools & Scripting

• Version control:

  ClearCase / Perforce

• Scripting:

  Perl, Tcl, Python

Experience

• 3 to 5 years

  in Digital Design Verification
• Must have worked on at least

  one full-cycle IP or SoC project

Education

• B.E / B.Tech / M.E / M.Tech

  in Electronics, Electrical, VLSI, or related fields

Additional Requirements

• Strong problem-solving and debugging skills
  
• Ability to work independently and in cross-functional teams
  
• Good communication and documentation skills
  

• Immediate joiners preferred