615 Design Verification Jobs - Page 9

Responsibilities: As a verification engineer with a knowledge of subsystems and SoCs you will make valuable contributions to a team tasked with verifying the functional correctness of SoC. Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy. Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules. Work with the Emulation/FPGA team in understanding various verification collaterals required for driving stimulus at the board level. Will collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, and FPGA and board development. Senior engineers are also encouraged to support junior members. Required Skills and Experience: 5 years of proven experience in working on IP/Subsystem/Soc Verification Experienced in Protocol on Flash Storage device Controller with unipro and MIPI PHY. Experience in Working on any of cross functional flows like Reset, Ras(Error and Interrupt), Security, low Power for High-speed IO IPs. Good Skills in System Verilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies UVM, formal and low power. Exposure to all stages of verification: requirements collection, creation of test plans, test bench implementation, test cases development, documentation, and support. Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools and Debuggers. “Nice To Have” Skills and Experience: Possess knowledge of object-oriented programming concepts Practical experience of working on Processor based system design Experience in Server/ Infrastructure SoC Strong understanding of CPU Architecture/micro-architectures!

You are a seasoned professional with a passion for analog design and a knack for solving complex problems- With a strong foundation in CMOS processes and deep submicron technologies, you bring a wealth of knowledge and experience to the table- You thrive in a collaborative environment, where your excellent communication skills enable seamless interactions with internal development teams- You are adept at executing circuit design tasks with precision, ensuring the highest product quality and efficiency- Your familiarity with ASIC design flow and JEDEC standards for DDR interfaces sets you apart, and you are always eager to learn and adapt to new challenges- Your technical acumen, combined with your dedication and innovative mindset, makes you an ideal fit for our team- What You ll Be Doing: - Ownership of complete physical implementation at block level & chip level- Responsible for delivering timing clean blocks/chip level that meet design targets- - DRC, LVS & IR closure- Evaluates all aspects of the physical design flow from place and route, timing, PV & IR and is able to setup these flows- - Experience in all chip level tasks (P&R, STA, PV, IR) - Work closely with the frontend design team to resolve design issues - The Impact You Will Have: Enhancing the performance and efficiency of our silicon IP portfolio- Contributing to the rapid integration of advanced capabilities into SoCs- Reducing the time-to-market and risk for our customers products- Driving innovation in analog design and setting new industry standards- Strengthening Synopsys position as a leader in chip design and verification- Empowering the development of high-performance, differentiated products- What You ll Need: - Candidates with MSEE/BSEE with 5+ years of related experience- Possesses in depth understanding of specialization area plus working knowledge of one other related area- - Resolves issues in creative ways- - Exercises judgement in selecting methods and techniques to obtain solutions- - Executes project responsibilities from start to completion- - Contributes to moderately complex aspects of a project- - Determines and develops recommendations to solutions- - Works on team-driven or task-oriented projects- - May guide more junior peers with aspects of their job- - Networks with senior internal and external personnel in own area of expertise- - Strong knowledge on scripting using tcl, perl - Who You Are: A collaborative team player with a proactive approach- Detail-oriented with a commitment to quality and efficiency- Innovative and adaptable, always seeking to learn and grow- Effective communicator, able to convey technical information clearly- Problem-solver with strong analytical skills- The Team You ll Be A Part Of: You will join a dynamic team of talented engineers dedicated to pushing the boundaries of analog design- Our team is focused on delivering high-quality silicon IP solutions that meet the unique performance, power, and size requirements of our customers- We foster a collaborative environment where innovation and continuous learning are highly valued- Together, we drive the development of cutting-edge technologies that shape the future of the semiconductor industry

Hi, Greetings from Thales India Pvt Ltd.....! We are hiring for Technical Lead - Design Verification (SV UVM) for our Engineering competency center for Bangalore location. Thales India Engineering Competency Center in Bangalore is seeking Technical Lead /Senior Technical Lead role to be part of AVS/FLX FPGA design and development team. In this role, you will be responsible for FPGA Validation & Verification for Avionics products and solutions. Responsibilities includes development of Test strategy, Virtual Verification Procedures, Test bench, BFMs, Monitors, Checkers & Virtual Verification Report as per DO254 guidelines. Qualifications: B.Tech/B.E or Masters in Electronics & Communication or equivalent with 8 to 12 years of relevant experience. Working experience in Defence\military\Aerospace products development is desirable Location: Thales India Private Limited, Richmond Town, Bengaluru, Karnataka 560025. Required Skills: Mandatory: Hands on in FPGA device Validation and Verification methodologies and processes. Experience in developing verification strategies and creating test plan based on requirements. Hands on Virtual Verification Environment development using VHDL and System Verilog/UVM Should be experienced in BFM development, monitors, checkers and Test case development using VHDL and SV/UVM Hands on with physical verification methodologies for various FPGA devices Good experience in Requirements Capture, developing Design Specification, Detailed design, Test procedure, Test report & other technical artefacts. Hands on experience in performing simulations using the Questasim tool. Should be hands on with configuration management tools such as GIT, BIT Bucket, DOORS, GIT/BIT Bucket/ REQTIFY/DOORS Good experience in RTL Design using VHDL, FPGA Implementation, Testing, Integration and delivery of FPGA based hardware systems for Defense\military\Aerospace Applications. Experience in any scripting language for automation, such as Python, Perl or TCL Experienced with Jenkins for continuous integration and automation of test and build processes. Capable of independently managing project planning, estimation, scheduling, technical risk identification and mitigation. Experience in Intel, Microchip or Xilinx based FPGA/PLD will have added advantage Experience in Bus Interfaces - A818, A429, SPI/UART/I2C, PCIe, AXI4, A664, LVDS, DDRx Should be experienced with environment to work in a cross-functional and multi-national global team. Expected to be Familiar: Experience in FPGA validation and verification in line with DO-254 process Experience in FPGA Implementation Tools (XILINX Vivado/ALTERA Libero SoC/ ALTERA Quartus). Experience in JIRA (Project / Issue management) Experience in handling Lab equipment (Logic Analyzer, Oscilloscope, Function Generators, JTAG, and In-circuit de-buggers).

As a Lead Hardware Design Engineer at TVSM Software Research & Development Organization, you will play a crucial role in defining and designing state-of-the-art hardware products that meet cost, reliability, and global standards by following best industry practices. You will collaborate with cross-functional teams to define hardware requirements for infotainment systems, VCU, and Telematics units, ensuring the development of cutting-edge architecture for hardware components that meet cost, reliability, and regulatory requirements. Your responsibilities will include working alongside hardware design engineers to create schematics, reviewing PCB layout plans and design, as well as Gerber files for thermal, EMI/EMC, signal integrity, and power integrity. You will also collaborate with PCB design engineers and mechanical engineers to deliver hardware according to customer requirements, perform reliability and costing analysis, and create design verification plans. Your role will involve conducting DFMEA with stakeholders, reviewing test reports, and collaborating with testing engineers for verification and validation of the designed hardware. To excel in this role, you must possess 8-12 years of expertise in automotive instrument cluster hardware design, with proven experience across all stages of the Hardware Product Development Lifecycle. You should be familiar with processors/controllers such as Renesas, NXP, ST, Microchip, TI, Qualcomm, MediaTek, and NXP, and have expertise in high-speed board design, multi-layer board design, signal integrity, power integrity, SMPS designs, high-voltage power design, analog and mixed-signal design. Furthermore, proficiency in interfaces like CAN, LIN, USB, I2C, UART, LVDS, MIPI, Automotive Ethernet, RF designs, SOC-based designs, and Chip on board designs is essential. Experience in homologation and RF certifications (EMI/EMC compliance) in Domestic and International markets, along with proficiency in tools like ORCAD, ALLEGRO, and ALTIUM, is required. Competency in using lab instruments like multi-meters, oscilloscopes, function generators, and logic analyzers, as well as ISO26262 certification and experience in AGILE methodologies, are important qualifications for this role. Advantageous experiences include design of functional safety ECUs meeting ISO26262 requirements, as well as experience in advanced technology projects like ARAS and Sensor fusion. Your behavioral competencies should include effective communication, assertiveness, innovation, creative problem-solving, and system-level thinking, while your leadership competencies should encompass leading innovation and diverse teams, adaptability, and strategic thinking. If you are looking to be a part of a technology-first organization dedicated to transforming consumer experience and increasing perceived value of products and services, this role offers a unique opportunity to drive innovation and excellence in hardware design for connected, safer, sustainable, and comfortable mobility solutions at TVSM Software Research & Development Organization.,

The Principal Structural Engineer is responsible for interpreting internal or external business issues and recommending best practices. You will be tasked with solving complex structural-related problems and working independently with minimal guidance. You may also be responsible for leading functional teams or projects and are regarded as a specialist in the field of structural engineering. It is essential to have in-depth expertise in structural engineering as well as broad knowledge of the structural discipline within the engineering function. Our ingenuity fuels daily life as we work together to forge trusted partnerships across the energy value chain. We have a history of making the impossible possible for over 100 years and are currently driving the energy transition with a team of over 30,000 bright minds across 54 countries. Key Tasks and Responsibilities include performing conceptual, FEED, and detailed analyses and designs according to project specifications and standards. You will need to apply your in-depth skills to address complex problems and nonstandard situations, prepare detailed design calculations and reports, manage your time effectively, and communicate difficult concepts clearly. When acting as Lead Engineer, you will also be responsible for directing medium or large engineering teams, leading discipline engineering design, planning resource requirements, and ensuring project deliverables are met according to schedule and budget. As a Principal Structural Engineer, you will be required to coordinate and check the work of senior and junior engineers, conduct peer reviews, provide technical assistance, and specialize in various fields and design codes. You will check designs for operational requirements, constructability, and maintainability, prepare project engineering guides, and work closely with project management. Additionally, you will be responsible for managing engineering subcontracts, identifying scope changes, filing engineering work, and providing relevant feedback to the department. You will report to Project Lead Engineer, Project Engineering Manager, or Project Manager, and liaise with various stakeholders such as engineering disciplines, construction sites, safety departments, project management teams, document control, procurement groups, subcontractors, and customers. Essential qualifications include a Bachelor's or Master's Degree in engineering, 15-20 years of experience in oil and gas, and proficiency in English. You should also be a seasoned professional with strong organizational, motivational, and problem-solving skills, along with a keen focus on improving work effectiveness, health, safety, and environmental practices. #LI-VA1,

Dear Candidate , Greeting from HCL Tech!!!!!!! We have come across your profile in Portal. Please Ignore if you already shared or submitted Details or Applied. As its a default retrigger. We are hiring on below Design Verification Engineer - Engineer/Lead/Senior Lead . Please find the JD Details below - Please share us your details below in Table with your update resume. JD - Design Verification Engineer - Engineer/Lead/Senior Lead Qualifications: Bachelors degree in electrical engineering, Computer Engineering, or a related field (masters degree a plus) Experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Please fill the details in below table Full Name (As per Passport/10th Class ) Highest Qualification(Distance/Regular) Total Exp Years Relevant Exp Years Exp Design Verification Engineer(Please specify) Years/Months Exp ASIC Years/Months Exp SOCS Years/Months Exp simulation tools : Please specify tools exp, which you hold Years/Months Exp scripting languages Years/Months Exp digital design principles Years/Months Exp verification methodologies (e.g., UVM) Years/Months Exp Verilog or VHDL Years/Months Mobile Number – Alternate Mobile Number – Mail ID Alternate Mail ID CTC ECTC (Please share expectation in number not in % or as per standards) Notice Period(Buyout options/on Bench/Currently serving(Please specify lwd) Current Company Current Location Have you attend Interview at HCL- Have you worked for HCL if Yes(Please share EX- HCL EMPID- Duration ) Preferred Location Reason for leaving Holding any offers /Any Pipeline :

Manage electronic document control and version control on all project-related documents.Ensure adherence to the quality systems, design assurance SOPs, and Boston Scientifics PLCP. Required Candidate profile Working on product DHF, design input, design output, product risk management, usability, verification, and validation efforts (if required) for commercial products.

We are hiring on below Design Verification Engineer/ RTL Design Engineer - Engineer/Lead/Senior Lead . Please find the JD Details below - Please share us your details below in Table with your update resume. Job Descriptions : Please specify for which role your application is for - DV/RTL JD - Design Verification Engineer - Engineer/Lead/Senior Lead JD - RTL Design Engineer- Engineer/Lead/Senior Lead Qualifications: Bachelors degree in electrical engineering, Computer Engineering, or a related field (masters degree a plus) Experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Qualifications: Bachelor’s degree in electrical engineering, Computer Engineering, or a related field (Master's degree a plus) Experience in RTL design for ASICs/SoCs Proven experience in designing and verifying complex digital circuits Proficiency in Verilog or VHDL Experience with verification methodologies (e.g., UVM) Strong understanding of digital design concepts (combinational logic, sequential logic, state machines) Experience with SDC (Standard Delay Constraint) format for timing closure Experience with scripting languages (e.g., Python, Perl) is a plus Excellent communication, teamwork, and problem-solving skills Benefits: Competitive salary and benefits package Opportunity to work on cutting-edge technologies Collaborative and fast-paced work environment Potential for professional growth and development

SENIOR VERIFICATION ENGINEER- SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience in SV/ UVM based verification project. Good debug skills is a must. Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment One of the following experiences is important: Experience in Video/Display domain in particular DP, oLDI, MIPI CSI/ DSI Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USADelaware

SR. VERIFICATION ENGINEER – SOC VERIFICATION SmartSoC is looking for smart and enterprising SOC Verification experts to come and work on complex SOC Verification projects. This role will include- Technical execution of SOC Verification projects of complex ARM based SOCs Test Planning, Environment Architecture, SV-UVM environments Desired Skills and Experience- 3 – 10 years experience in Design Verification Excellent Communication and Presentation Skills Expert Knowledge in SOC Verification Expert at Verification – Coverage Driven Test Planning, Architecting Environments, Verification Flow Strong knowledge in System Verilog Knowledge in at least one methodology, OVM, UVM, VMM or RVM Very Good knowledge of protocols, at least one protocol of SATA, USB, Ethernet, PCIE Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida SwedenStockholm USATexas

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 8 – 12 years experience in Design Verification Expert Knowledge in IP Verification Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface Must have expert knowledge in coverage driven test planning Must have expert knowledge in architecting configurable environments Must have very strong System Verilog and UVM background Must be able to lead the team technically in all aspects, must be able to drive multiple projects Past experience leading and managing teams highly desired Excellent Communication and Presentation Skills Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). The primary focus of this role will be on Ethernet protocol verification, ranging from 100G to 800G standards. Key Responsibilities: Ethernet Protocol Expertise Demonstrate expertise in Ethernet standards, encompassing 100G to 800G. In-depth knowledge of specific standards, including 100GE (cl45, cl49, CL82, CL91, CL119), 200GE, 400GE (cl161, cl116), and 800GE (802.df/800ETA). Proficiency in PTP 1588 standard and various Ethernet frame types. Competence in packet insertion/extraction techniques. (Additional knowledge of AXI protocol would be considered an advantage) UVM/SV Proficiency Showcase strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM). Architectural Skills Proven ability to architect, build, and maintain a comprehensive verification stack. Test Development Extensive experience in developing a set of regression tests for verification purposes. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). Excellent understanding of Ethernet protocols, ranging from 100G to 800G. Proficiency in PTP 1588 standard and various Ethernet frame types. Experience with packet insertion/extraction techniques. Knowledge of AXI protocol (preferred). Proven ability to architect, build, and maintain verification stacks. Demonstrated expertise in developing a comprehensive set of regression tests. If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of cutting-edge technology, we encourage you to apply. Join our dynamic team and contribute to the advancement of next-generation technologies. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience Level: Over 4 years Location: Bangalore Skills: Proficiency in SystemC, C++, and SV/Verilog, coupled with hands-on coding experience in these languages. Strong aptitude for debugging and effective communication. Familiarity with scripting languages (desirable). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

We are seeking a highly skilled and experienced Lead Verification Engineer with expertise in USB/LPDDR and a strong knowledge of Cadence VIP. The ideal candidate will have a deep understanding of low-power design and verification techniques. Responsibilities: Develop and execute comprehensive verification strategies for USB/LPDDR subsystem designs, considering low-power design requirements. Collaborate with cross-functional teams to define verification goals and ensure alignment with project objectives. Design and implement reusable, scalable, and efficient verification testbenches using SystemVerilog/UVM or C based . Leverage Cadence VIP and other verification IPs to accelerate the verification process. Low-Power Design VerificationApply expertise in low-power design and verification techniques to ensure accurate and reliable verification of power management features, including power states, power domains, and power-aware verification methodologies. : Extensive experience (8+ years) in verification. Strong knowledge of Cadence VIP and verification methodologies (SystemVerilog/UVM). Proficiency in low-power design techniques and power-aware verification methodologies. Hands-on experience with industry-standard simulation and verification tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa). Solid understanding of verification languages (SystemVerilog, VHDL) and scripting languages (Perl, Python, TCL). Familiarity with industry standards and protocols related to USB (USB 2.0, USB 3.x) and LPDDR (LPDDR4, LPDDR5). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience Level: 8+ years Location: Bangalore/Hyderabad Skills: Profound expertise in MACSec and Ethernet technologies. MACSec (Media Access Control Security): Proficient in point-to-point security implementation on Ethernet links, adhering to the IEEE 802.1AE-2018 standard. IPsec (Internet Protocol Security): Skilled in establishing security between two devices across an Internet Protocol network. Hands-On Knowledge: Proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), with practical experience in their application. Testbench Development: Demonstrated experience in developing comprehensive Test Benches (TB) and individual verification components. Communication and Leadership: Possesses excellent communication skills and adept at leading and coordinating teams effectively. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification and possess a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). This role specifically requires expertise in GLS (Gate-Level Simulation). Key Responsibilities: IP and SOC Verification Conduct IP and SOC verification activities to ensure the functionality and correctness of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate strong knowledge of SystemVerilog and Universal Verification Methodology for efficient and effective verification processes. Gate-Level Simulation (GLS) Proficiency in Gate-Level Simulation is a mandatory requirement for this position. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM). Proficiency in Gate-Level Simulation (GLS). If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of integrated circuits, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly experienced Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong foundation in SystemVerilog (SV) and Universal Verification Methodology (UVM). In addition to standard verification skills, this role requires expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST (Memory Built-In Self-Test), SCAN, PG (Pattern Generator), and PM (Pattern Memory). Key Responsibilities: IP and SOC Verification Perform comprehensive IP and SOC verification to ensure the reliability and functionality of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate a strong understanding of SystemVerilog and Universal Verification Methodology for efficient verification processes. CDP, GDP, DFT DV Expertise Possess expertise in Compressed Data Pattern (CDP) and Generic Data Pattern (GDP) methodologies. Proficiency in Design for Test in Design Verification (DFT DV) techniques, including JTAG, MBIST, SCAN, PG, and PM. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong knowledge of SystemVerilog (SV) and Universal Verification Methodology (UVM). Expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST, SCAN, PG, and PM. If you are a talented Design Verification Engineer with a deep understanding of IP and SOC verification, as well as specialized expertise in CDP, GDP, and DFT DV methodologies, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Number of Open Positions: 7 Location: Bangalore Experience: 4 to 7+ years : We are currently seeking talented and experienced Design Verification Engineers to join our team in Bangalore. As a Design Verification Engineer, you will be responsible for ensuring the functionality, performance, and reliability of our complex designs, with a focus on Core Data Path (CDP), Graphics Data Path (GDP), USB4 (USB 4.0), Power Gating (PG), and Power Management (PM) domains. We are looking for candidates with 4 to 7+ years of relevant experience in design verification. Key Responsibilities: Verification Planning: Collaborate with design and architecture teams to develop comprehensive verification plans for CDP, GDP, USB4, PG, and PM components. Testbench Development: Create and maintain advanced testbenches, including constrained-random and assertion-based methodologies, to thoroughly verify design functionality. Functional and Coverage Testing: Execute functional tests and track coverage metrics to ensure exhaustive testing of design features. Protocol Verification: Verify compliance with industry-standard protocols, including USB4, and identify and address protocol violations. Bug Reporting and Debugging: Document and report issues, and work closely with design teams to resolve bugs in a timely manner. Performance Verification: Assess and verify the performance of data path components, ensuring they meet specified requirements. Power Verification: Verify power management and power gating strategies to optimize power consumption. Scripting and Automation: Develop and use scripting languages and automation tools to streamline verification processes. Documentation: Prepare detailed verification plans, test reports, and documentation. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. 4 to 7+ years of experience in design verification. Strong knowledge of CDP, GDP, USB4, PG, and PM domains. Experience with industry-standard verification methodologies and tools. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. If you are a highly motivated and detail-oriented Design Verification Engineer with a passion for ensuring the quality and reliability of complex designs, we encourage you to apply. Join our team to work on cutting-edge technologies and contribute to the success of our projects. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Take the lead in advanced design verification!Were looking for a Senior Design Verification Engineer in Bangalore to work onHBM, DDR, UCIe, PCIe protocols, and more.Key Skills: System Verilog/UVM, protocol verificationExperience Required3+ YearsJoin our team and help shape groundbreaking designs. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Number of Open Positions4 Experience: 4+ years Location Hyderabad : We are looking for a highly skilled and experienced Gate-Level Simulation Engineer to join our team. The ideal candidate should have a minimum of 4 years of experience and possess a strong background in gate-level simulation (GLS). Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM) is essential for this role. Key Responsibilities: Collaborate with cross-functional teams to define and execute gate-level simulation test plans. Develop and implement gate-level simulation strategies for complex digital designs. Conduct gate-level simulations to verify the functionality and performance of digital designs. Work closely with design and verification teams to identify and resolve issues at the gate level. Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process. Ensure compliance with industry standards and best practices in gate-level simulation. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 4+ years of experience in gate-level simulation. Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). Prior experience in gate-level simulation is essential. Familiarity with gate-level simulation tools and methodologies. Excellent problem-solving skills and attention to detail. Effective communication and collaboration skills. Ability to work in a dynamic and fast-paced environment. If you are a motivated and experienced Gate-Level Simulation Engineer with a strong background in SV, UVM, and a passion for ensuring the quality and reliability of digital designs at the gate level, we encourage you to apply for this position. Join our team and contribute to the success of our cutting-edge projects. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaHyderabad

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: Minimum 8 years of experience in functional Design Verification (DV) Proficiency in low-power UPF-based verification Strong debugging skills Skills: In-depth understanding of power gating and power management techniques Familiarity with AXI and SMN protocols Previous experience with AMD is advantageous Location: Hiring for Bangalore (BLR) or Hyderabad (HYD) locations NotePlease provide a detailed resume highlighting relevant experience and skills. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Let your ideas power the next wave of technology!Were hiring Design Verification Engineers for Bangalore and Hyderabad.Experience Required4"“18 YearsKey Skills: HSIO protocols like PCIe, DDR5, HBM, USB, low-power simulationsWork on cutting-edge verification projects and take your career to new heights. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Job Description: We are hiring Verification Engineers with expertise in SoC and IP verification for a 1-year contract role in Bangalore. Key Responsibilities: Develop C-based test cases and perform Subsystem/SoC verification Conduct IP verification using UVM methodology Handle complete verification flow planning, testbench implementation, and coverage closure – Debug and resolve issues efficiently – Work on ARM-based designs and protocols (AMBA APB, AXI, CHI) – Port peripheral driver software for SoC test cases – Perform GLS, DFT/DFD, and Power Aware verification Desired Candidate Profile: – Experience: 3–5 years (Mid-Level) / 5+ years (Senior-Level) – Contract Duration: 1 year – Location: Bangalore (Onsite) – Notice Period: Immediate to 15 days preferred

You are invited to join Qualcomm India Private Limited as an IP Design Engineer within the Engineering Group > Systems Engineering team. As a highly skilled professional with a background in microarchitecture design and RTL design for complex IPs, you will play a key role in the development of innovative IP solutions, ensuring high-quality and reliable designs. Your main responsibilities will include leading the design and development of IP solutions from scratch, collaborating with cross-functional teams to define design specifications, ensuring design quality and performance through PLDRC and synthesis processes, maintaining detailed documentation, troubleshooting complex design issues, and staying up-to-date with industry trends and best practices. To excel in this role, you should possess 7-10 years of experience in IP design, with a focus on microarchitecture and RTL design, extensive hands-on experience with AMBA or PCIe protocols, proficiency in PLDRC and synthesis tools, a strong understanding of digital design principles, experience with design verification and validation, excellent problem-solving skills, and the ability to work independently and in a team environment. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is required. Preferred skills include experience with industry standard design flow tools, knowledge of ASIC design flows, familiarity with scripting languages like Python for automation, and experience with version control systems like Git and clearcase. Qualcomm is an equal opportunity employer committed to providing accommodations for individuals with disabilities during the application/hiring process. If you require an accommodation, please contact disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures to protect confidential and proprietary information. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through this site. Unsolicited submissions will not be accepted. For more information about this role, please contact Qualcomm Careers.,

We are hiring PCIe engineers: -In-depth knowledge and experience with PCIe protocols upto Gen5 -Good experience of system Verilog -handson experience of working on UVM -Good to have scripting language Perl/Shell/python