408 Design Verification Jobs - Page 13

Transport is at the core of modern society. Imagine using your expertise to shape sustainable transport and infrastructure solutions for the future? If you seek to make a difference on a global scale, working with next-gen technologies and the sharpest collaborative teams, then we could be a perfect match. We value your data privacy and therefore do not accept applications via mail. Who we are and what we believe in We are committed to shaping the future landscape of efficient, safe, and sustainable transport solutions. Fulfilling our mission creates countless career opportunities for talents across the group s leading brands and entities. Applying to this job offers you the opportunity to join Volvo Group . Every day, you will be working with some of the sharpest and most creative brains in our field to be able to leave our society in better shape for the next generation. We are passionate about what we do, and we thrive on teamwork. We are almost 100,000 people united around the world by a culture of care, inclusiveness, and empowerment. Group Trucks Technology are seeking talents to help design sustainable transportation solutions for the future. As part of our team, you ll help us by engineering exciting next-gen technologies and contribute to projects that determine new, sustainable solutions. Bring your love of developing systems, working collaboratively, and your advanced skills to a place where you can make an impact. Join our design shift that leaves society in good shape for the next generation. Key Responsibilities: Design and development of Chassis Structures such as frame rails, cross members, multi-function brackets, installation of driveline components on Chassis. Delivers value through creation of design concepts by balancing of cross functional needs, collaborating with suppliers to co-develop product solutions. Work closely with colleagues in different Volvo Group global sites, cross functional teams to develop the system and its parts. Development of vehicles structures based on BEV / ICE / alternate energy propulsion systems. Carryout vehicle packaging, durability verification and physical validation needs. Come up with optimized design solutions while working with FE simulation analysts. Work closely with project managers and cross functional teams to anticipate process steps and propose mitigation plans for identified risks. Engineering documentation of drawings, technical requirement, functional specification and managing change. Education, Skills and Experience: BE/ME - Mechanical/Automobile Engineering equivalent with 3 to 6 years of relevant work experience. Hands-on work experience in truck chassis aggregates / equipment installation. Strong in structural design, being analytical and problem-solving ability. Knowledge of design verification and validation is required. Good knowledge of application of GD&T. Extensive hands-on experience in Creo and PDM software, exposure to vehicle packaging is required. Additional requirements: Good networking and interpersonal skills with good verbal and written English communication. Process oriented way of working and a team player mindset are success factors in this role. Be able to recognize the value and importance of providing solutions with the right quality level and on time.

RTL engineers: (5-15 years of experience) - SoC Design engineer with experience working on SOCs based on ARM Architecture DV engineers : - SOC Verification Experience on ARM Ecosystem - PCIE Experience and also PCIE-VIP usage experience

Design Verification Engineer (5 to 12 Years) SoC/IP Verification Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune] Experience: 5 t o 12 Years Openings: 8 Positions Preferred - Immediate to 45 Days (Notice Period) Job Location: ACL Digital is hiring experienced Design Verification Engineers to work on leading-edge processor-based SoCs and IPs. Notice Period-Prefer less Notice period or serving. Strong understanding of design verification methodologies (UVM, SV, etc.) Experience with industry-standard protocols (AXI, DDR, PCIe, etc.) Familiarity with ASIC and SoC design flows. Proficiency in scripting languages (Python, Perl) Experience with simulation tools and debuggers. Strong problem-solving and analytical skills Communication and collaboration skills to work effectively with cross-functional teams Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: AMBA, AXI, PCIE, USB, MIPI

An RTL Design Verification Engineer role in our Security IP (SECIP) development team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our verification engineers will work on block level functional verification and its closure, and/or on subsystem level integration and verification for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications. The person: A talented hardware/firmware co-design/verification engineer with strong records of technical ownership and execution to drive block level IP and/or MP subsystem design and verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. Key responsibilities: Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructure Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology, C-DPI directed test methodology, formal proof verification methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure Participate in MP subsystem specification, influence IP micro-architecture development (design for verification aspect), design and execute reusable test methodology across individual MP subsystems Debug and solve integration issues with SoC Integration and SoC DV teams Provide technical leadership in verification methodology development and critical problem resolution if as advanced level team members Provide project execution leadership in term of technical assignment ownership, technical mentorship, task planning through divide and conquer, task progress reporting and forecasting if as advanced level team members Preferred experience: BSc with a minimum of equivalent 5 years relevant experience; or MSc with a minimum of equivalent 3 years; or PhD in a directly related research area and a minimum of 1 year A minimum of equivalent 10 years relevant experience if as advanced level team members Proven understanding of MP subsystem and/or common hardware datapath accelerator architectures as well as deep knowledge of applicable state-of-art verification methodology and best practices, if as advanced level team members Proficient in System Verilog, object oriented programming, and scripting (using Ruby, Perl, Python and Makefile) Proven skills in creating UVC and other UVM components. Experience with C-DPI and Formal Verification techniques are valuable assets. Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA) Proven experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc. Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates Academic credentials: Bachelors Degree or Masters Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field Masters Degree preferred

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 8 – 12 years experience in Design Verification Expert Knowledge in IP Verification Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface Must have expert knowledge in coverage driven test planning Must have expert knowledge in architecting configurable environments Must have very strong System Verilog and UVM background Must be able to lead the team technically in all aspects, must be able to drive multiple projects Past experience leading and managing teams highly desired Excellent Communication and Presentation Skills Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SENIOR VERIFICATION ENGINEER – SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience in SV/ UVM based verification project. Good debug skills is a must. Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment One of the following experiences is important: Experience in Video/Display domain in particular DP, oLDI, MIPI CSI/ DSI Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USADelaware Location - Bengaluru,Chennai,Hyderabad,Noida

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Mumbai,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. This position is within the process diagnostics and control (PDC) group, which deals with advanced imaging together with cutting edge image processing algorithms and design CAD in order to detect, measure and classify nanometer size defects from semiconductor fabrication process steps. Application engineers are supposed to maximize the performance of our new defect metrology products through a deep and thorough understanding of use-cases in close technical collaboration with leading-edge chip manufacturing customers. Build and maintain strong relationships with customers, including regular communication, feedback and follow-up to ensure customer satisfaction and success. Work closely with internal Product teams including R&D, marketing and internal Account stakeholders to ensure alignment, effective communication and customer engagement. At a higher expertise level, they also contribute to product development roadmap through spec definition and performance validation. They also contribute to SW Application Alpha/Beta phase of qualification in-house and at customer site. Desired qualification Masters / Bachelors degree in Electrical/Electronics Engineering, Mechanical Engineering, Computer Science Engineering or in a related field. 2 to 5 yrs experience in Semiconductor Design, Design Verification, Fabrication or in related field, with focus on technical support, training and/or product development. Sound fundamentals of high-NA DUV imaging/SEM and light-matter/electron-matter interaction Open to on average 50% travel to leading semiconductor chip manufacturing fabs overseas Lab/fab hands-on experience in semiconductor fabrication with layer-wise detailed knowledge of material, process tech and defectivity Detail oriented with strong analytical, problem solving and communication skills Ability to work in a team, and ability to work independently Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 50% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job responsibilities: BE/BTECH/ME/MTECH Or Equivalent Degree EXP:10-18yrs Primarily working for Roadmap project MRDIMM Controller for CHI Address channel Multiplexing RTL Design, Verification and Synthesis Support. Work to achieve MRDIMM Controller for CHI Address channel Multiplexing Feature s Optimal PPA (Performance, Timing and Area) We re doing work that matters. Help us solve what others can t.

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

Responsibilities: SoC integration/scenario/performance verification including CHI, DDRx/LPDDRx, and AI accelerator blocks in RTL. Develop test plans, SystemVerilog/Verilog testbenches, and C-based embedded tests. Collaborate with cross-functional teams architecture, design, performance, silicon validation, FPGA, and board teams. Plan, track and report verification tasks to management. Skills & Experience Required: Strong knowledge of Verilog/SystemVerilog HDL. Hands-on experience in SoC verification using embedded C/C++/assembly (ARM preferred). Experience in UVM/OVM, emulation, formal verification, UPF/Power-aware verification. Expertise in GLS, DFT/DFD, CDC (Clock Domain Crossing). Familiar with ARM SoC boot flows, cache coherency, SoC verification flow & strategy. Scripting experience in Python, Perl, Tcl, Shell. Excellent debugging and problem-solving skills.

Role & responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Preferred candidate profile Bachelors/ Masters degree or higher in EEE/ECE 4+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Position Title: Manager/ Sr Manager Functional Safety, SOTIF Experience: 12 ~ 15 Year(s) Age Limit Educational Qualification B.E / B. Tech Job Role Responsibilities Role: Taking care of Functional Safety and Software Update Team activities. Responsibilities: Management of Functional Safety Management of Software Update team Functional Safety Software Update Consulting and Promoting to each department. Can provide functional safety guidance on feature definition, design, verification and validation measures. Collaboration with Cross-Functional Teams to work closely with other engineering disciplines (such as software, hardware, and mechanical engineers) to ensure safety across the entire system. Collaborate during system development, validation, and verification phases. Perform Confirmation reviews on SOTIF workproducts Prepare assessments based on requirements Process/templates/checklists for SOTIF to be defined for MSIL use Systematically derive relevant scenarios, evaluate in terms of damage severity and controllability Derive measures to ensure a safe target function. Carrying out residual risk analyses Documentation of existing considerations and analyses regarding SOTIF The SOTIF engineer shall be very familiar with ISO 21448 Manage safety requirements traceability and work with design, implementation, performance, validation and service team members to validate SOTIF requirements. Competency Requirements Must possess good experience in Design field. Should be aware of technicalities of designing a part and ought to be capable of verifying the modifications introduced in the same as per regulatory standards. Enthusiasm and a desire to work in a very fast-paced environment where innovation and rapid change is the norm. Strong system engineering background Good interpersonal and communication skills with a high level of integrity Experience working within a cross-functional team Expert knowledge of ISO 21448 (preferable) Lead with confidence. Preferably proven track on technical leadership Behavioral: Capability of managing a Team having variety of projects. Have grip over latest Industrial Trends (global domestic) and innovatively avail the same in respective work domain. Have ability to effectively plan and co-ordinate mutual activities with various stakeholders. Should possess good Interpersonal, Communication Presentation skills.

Role: Taking care of Functional Safety and Software Update Team activities. Responsibilities: Management of Functional Safety Management of Software Update team Functional Safety Software Update Consulting and Promoting to each department. Can provide functional safety guidance on feature definition, design, verification and validation measures. Collaboration with Cross-Functional Teams to work closely with other engineering disciplines (such as software, hardware, and mechanical engineers) to ensure safety across the entire system. Collaborate during system development, validation, and verification phases. Perform Confirmation reviews on SOTIF workproducts Prepare assessments based on requirements Process/templates/checklists for SOTIF to be defined for MSIL use Systematically derive relevant scenarios, evaluate in terms of damage severity and controllability Derive measures to ensure a safe target function. Carrying out residual risk analyses Documentation of existing considerations and analyses regarding SOTIF The SOTIF engineer shall be very familiar with ISO 21448 Manage safety requirements traceability and work with design, implementation, performance, validation and service team members to validate SOTIF requirements. Must possess good experience in Design field. Should be aware of technicalities of designing a part and ought to be capable of verifying the modifications introduced in the same as per regulatory standards. Enthusiasm and a desire to work in a very fast-paced environment where innovation and rapid change is the norm. Strong system engineering background Good interpersonal and communication skills with a high level of integrity Experience working within a cross-functional team Expert knowledge of ISO 21448 (preferable) Lead with confidence. Preferably proven track on technical leadership Behavioral: Capability of managing a Team having variety of projects. Have grip over latest Industrial Trends (global domestic) and innovatively avail the same in respective work domain. Have ability to effectively plan and co-ordinate mutual activities with various stakeholders. Should possess good Interpersonal, Communication Presentation skills.

Introduction As a Hardware Engineer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in todays market. Your role and responsibilities Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification : Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Engineer must possess strong understanding on SoC Verification. Engineer must be having 5+ Years of Design Verification Understanding. Engineer must be fluent in Verilog, C/C++, SystemVerilog. Design Debugging skill is mandatory.

Engineer must possess strong understanding on IP & SoC Verification with 7+ Years of Design Verification Exp. Must possess string understanding on Verilog, SystemVerilog, C/C++. Must be able to debug the failure and able to narrow down the root cause.

. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. . 3-10 years of experience in RTL design and Design Verification implementation for VLSI systems.

Working on Functional Verification of High-Speed PHY IPs for DDRxx, LPDDRxx, PCIex, Display, and HDMI protocol standards. Studying IP/design blocks/Firmware Specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Developing DV/Firmware test benches, test plans, and test cases. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs). Performing simulation, random and focused stimulus generation, and coverage analysis. Collaborating closely with digital designers for debugging and achieving desired coverage. Developing architecture and micro-architecture knowledge of complex digital design blocks under test. The Impact You Will Have: Ensuring the high quality and reliability of our High-Speed PHY IPs. Contributing to the successful delivery of cutting-edge technology solutions. Enhancing the performance and functionality of our products through rigorous verification. Driving innovation and excellence in our verification processes. Supporting the rapid integration of capabilities into SoC designs. Enabling our customers to bring differentiated products to market quickly with reduced risk. What You'll Need: B. Tech/M. Tech in EC/CS with 3-6 years of relevant experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs. Understanding of functional verification flow with experience on industry-standard development and verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in System Verilog Assertions, code and functional coverage implementation, and review. Excellent debug and diagnostic skills. Experience with scripting and automation using TCL, PERL, or Python.

Greeting with HCL Tech! We were looking somebody who is having experience in Design Verification Experience: 4 to 10 Years Location: Kochi Job Description: General verification expertise System Verilog. UVM Understanding of ARM processor based SOCs, AXI / AHB Good knowledge of Processor based C tests for SOC verification (test coding, compilation, loading in TB, failure debug) Strong hands on work experience of test development, simulation along with usage of popular EDA tools Good debug skills – Check that engineer has done reasonable amount of debug in past projects Has logical and methodical approach to debug issues /failures Has used standard tools for debugging, as applicable

Introduction As a Hardware Engineer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in todays market. Your role and responsibilities Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 1-3 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification : Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Role & responsibilities Job Responsibility As the Lead, you will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, test cases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support. You will work very closely with the Architecture, RTL/uArch, and cross-functional teams. Areas of focus: Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with the RTL/uArch team. Job Requirements Experience with block level, cluster level or chip/SoC level verification. Should be a self-starter. Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog. Expertise in scripting languages, python or perl. Strong experience in helping emulation and validation. Experience with modeling various HW blocks, IPs for verification, emulation. Ability to analyze systems-level performance, profiling, and analysis. Post silicon support Preferred candidate profile

ASIC Design Verification Engineer || UVM/System Verilog || Test benches || Exp 4 to 7 years Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Ciscos revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch for block and cluster level environments. Maintain and enhance existing DV environments. Develop test plans and tests for qualifying design at block, and cluster level environments with mix of constraint random and directed stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and optimal performance. Support testing of design in emulation. Minimum Qualifications Bachelors Degree in EE, CE, or other related fi eld. 5+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying complex blocks and/or clusters for ASIC. Experience building test benches from scratch, hands on experience with SystemVerilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, Qualifications: Minimum Qualifications: BE/Btech/MTech with 6 Plus years of experience Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Create plans and tests for validating portions of a complex microarchitecture using written specs, RTL code, Firmware and other tests as a guide Experienced with the architecture, microarchitecture and Power Management flows and debugging failures to the root cause Develop and utilize various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design Participate in the debug of failures on silicon and develop new testing strategies to detect these failures on RTL models Develop tools and methods to streamline validation of PM flows, PM HW/FW interactions, and SOC level validation to deliver highest quality design in shortest time possible. Job Type: Experienced Hire

Strong knowledge in SV,UVM Skills: SOC/IP Verification Protocol: Ethernet/PCIe Experience: 4+ Years Should have Scripting knowledge Need experience in 2 tape outs projects