Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: About The Role : Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. o BE/BTech degree in CS/EE with 3+ years"™ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologies:JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3+ years of experience in Design Verification. Hands on experience in SOC level test bench and test plan development. Good knowledge of UVM, System Verilog, PSS Knowledge of Amba Protocols such as CHI, ACE. Hands on experience in PCIe, USB4, DDR4/5 Experience in bare metal post silicon Good Communication.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Principal Duties & Responsibilities Responsible for creation of "State of the art" UVM based verification test benches and methodologies to verify complex IP"™s and Sub-Systems. Define testplans, tests and verification infrastructure for modules, clusters and systems. Exposure to Power Aware Verification will be a plus. Build efficient and reusable bus functional models, monitors, checkers and scoreboards. Implement Functional coverage and own verification closure. Work with architects, designers, emulation and post silicon teams verification completeness. Good debugging & analytical skills. "¢ Applies advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry independently; has a basic understanding of other domains. "¢ Reads device specification sheets and interprets complex details required to design various hardware features; provides guidance to less experienced engineers working with spec sheets. "¢ Identifies advanced ways to optimize tests and/or hardware designs by evaluating device performance over a wide range of operating conditions and configurations. "¢ Evaluates complex design features to identify potential flaws (electrical, mechanical, hardware), compatibility issues, and/or compliance issues; advises less experienced engineers on design evaluations. "¢ Documents complex details about materials, components, chipsets, and functionality for a device while being mindful of potential compatibility, safety, and compliance issues; assists less experienced engineers in their documentation of these details. "¢ Troubleshoots advanced issues with product designs and finds solutions that are documented and shared with internal teams working on similar products. "¢ Provides essential technical input, support, and documentation for internal customers; advises less experienced engineers on how to provide support for clients. "¢ Acts as a tech lead on mid-sized to large projects and owns the outcome of the project. "¢ Manages project-related activities (e.g., meetings, documentation, deliverables) between their team and other teams working on the same or similar products, operating across locations and time zones; brings the project to conclusion. "¢ Utilizes deep understanding of Qualcomm products to evaluate and test hardware designs and identify unique components or functions that could potentially be filed for IP patents; shares these findings with their manager. "¢ Displays deep knowledge in a specific area; acquires advanced knowledge of industry trends, competitor products, and advances in various engineering fields from publically available information; shares knowledge with others on team and helps less experienced engineers understand and apply advanced concepts. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Description Seize the opportunity to work with the team responsible for RTL logic design and development of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for ISCP client projects. This job requisition is to seek an experienced, disciplined and collaborative design verification engineer in Bangalore, India. As a member of the Chipsets Logic Design Verification team, you will work closely with IP architects to define and develop verification testbench and building RTL models for verification. You will be validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools. You will be finding and implementing corrective measures for failing RTL tests, analyzes and uses results to modify testing. Your influence will cross organizational boundaries with our manufacturing and validation partners. Your expertise will grow as you debug and resolve issues on system platforms using software and RTL simulation tools. Qualifications The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : UVM, AMBA protocols, system verilog, IP sub-system DV. Other technical requirements: 3 to 8 years of relevant pre-silicon verification/logic design experience. Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/Shell scripting, power-aware simulation with VCS/Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in developing test plan and contents and coverage points for validation purpose based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology, SIP and HIP interoperability validation. Experienced in Power-aware design and validation flows. Experienced in AMBA, UFS, SPI, USB, PCI express or any industry standard BUS protocol. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

Job Description Seize the opportunity to work with the team responsible for RTL logic design and development of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for ISCP client projects. This job requisition is to seek an experienced, disciplined and collaborative design verification engineer in Bangalore, India. As a member of the Chipsets Logic Design Verification team, you will work closely with IP architects to define and develop verification testbench and building RTL models for verification. You will be validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools. You will be finding and implementing corrective measures for failing RTL tests, analyzes and uses results to modify testing. Your influence will cross organizational boundaries with our manufacturing and validation partners. Your expertise will grow as you debug and resolve issues on system platforms using software and RTL simulation tools. Qualifications The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : UVM, AMBA protocols, system verilog, IP sub-system DV. Other technical requirements: 3 to 8 years of relevant pre-silicon verification/logic design experience. Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/Shell scripting, power-aware simulation with VCS/Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in developing test plan and contents and coverage points for validation purpose based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology, SIP and HIP interoperability validation. Experienced in Power-aware design and validation flows. Experienced in AMBA, UFS, SPI, USB, PCI express or any industry standard BUS protocol. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel's offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements. Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Design verification plans and develop, maintain UVM testbench components. Gain a deep understanding of the design and testbench under your responsibility. Build UVM testbenches, including writing tests, sequences, checkers, scoreboards, and verification/coverage plans. Take ownership of task definition, effort estimation, and progress tracking. Contribute to the improvement and evolution of GPU verification methodologies. Take ownership of coverage closure and provide verification metric reports. About you You\u0027ll have: Experience in developing and maintaining verification components. Strong proficiency in SystemVerilog, UVM, and constrained-random verification methodologies. Skilled in debugging and identifying root causes of issues. Effective communication of technical issues, both verbally and in writing. You might also have: Knowledge of Graphics, GPU, CPU, or SoC architectures. Experience with broader verification technologies, including formal property-based verification (FPV). Proficiency in coding and scripting using Python, TCL, Perl, SystemC, or C++

About The Role : Performs functional logic verification of a block, subsystem, and SoC related to DCAI flagship AI products to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 10+ years of technical experience. Related technical experience should be in/with:Silicon Design and/or Validation/Verification. Preferred Qualifications: Design/Verification with developing, maintaining, and executing complex IPs and/or SOCs. Design/Verification exposure for PCIe Subsystem involving full protocol stack - Transaction layer, Data Link Layer and PHY Layer Design/verification exposure for Industry standard BUS topologies such as AMBA AXI/AHB/APB, I2C, SPI, JTAG, CoreSight Debug and Trace OVM, UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

General Summary: The role generally entails a mixture of: Ownership of a piece of the test bench Planning & execution of feature additions and mode re-enablement on particular variants Bug fixes Debug of regression signatures Developing/Deploying new tools for performance validation Performance monitor and profiler development and deployment Workload specific simulations on the emulator Following skillset is required: Strong Python, C++ skills Reading Specs and developing test plans Monitors, scoreboards, sequencers, and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening 6 months - 1 Year of industry experiences in the following areas: - Basic of digital design concepts, fifo etc Basic understanding of DDR is a plus Understanding of interconnect protocols like AHB/ AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization Minimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer Engineering Candidate must possess right analytical skills, debug oriented mindset and must be open to discuss , deep dive, collate and present the design and environment understanding . Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/ Analog/ RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm SoC Verification Engineer The candidate will be responsible to own SoC Interconnect DV (Connectivity matrix, Coherency, Clock gating, Performance etc) during the project work. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams. Skillsets / Requirements : B.E/B.Tech/ M.E/M.Tech in Electronics with 7+ year experience in verification domain. Good understanding of Soc level verification testbench and flows. Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc. Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI. Solid hands-on working experience on System Verilog and UVM methodology. Expert in handling protocol BFM/ VIP integration and traffic sequence development. Experience in coding assertions and functional coverage bins. Qualcomm Power DV Engineer We are looking for passionate, highly motivated, and creative individuals to be part of our Power Verification team. As the power team member, you will work on projects that will define the next generation of Modem, Mobile, XR/VR and Automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's, cutting edge power optimization techniques, Functional safety aspects and many other leading technologies deployed in our Snapdragon chips. General Summary Qualcomm Power DV team is responsible for the verification of Power Controller sub-system that powers up/controls the clock/voltage/ operating level/power for the entire SoC. Along with the complex power controllers, the team is responsible for verification of various sensors and the respective controllers, Power limits management IPs and the IPs interacts with the external PMIC. In the role of Power Verification Engineer, you are expected to understand the Low power design functionality and verification strategies and driver the overall SoC low power verification. The Responsibilities Will Majorly Include Understanding of SoC power domains and HW programming guide sequences Develop test plan to verify all low power aspects across all modes of verification RTL, PA-RTL, PA-GLS and Formal Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals Participate in post Si debug and bring-up activities Exploring innovative dynamic or static methodologies by engaging with EDA vendors Work with architects, designers, FPGA and post-silicon teams to ensure that the IPs are verified/validated thoroughly. Preferred Qualifications: Strong System Verilog/ UVM based verification skills & Experience with Assertion & coverage-based verification methodology Good understanding of low power design techniques Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells. Experience with UPF/CPF based power aware verification. Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus Bus protocols (AHB/ AXI/APB) C/C++ with any ARM core knowledge Exposure to Formal/Static verification methodologies and Post-Si debugs would be excellent Good debugging and analytical skills. Good interpersonal skills, ability to work as an excellent teammate Excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization BTech/MTech with below years of experience in verification closure of complex Unit, Sub-system or SOC level verification. 5 To 12 Years of experience to lead Power DV of one or more SoCs Qualcomm SOC DV Engineer (MM) As a DV Engineer with a focus on SOC design verification, you will work to understand the internal requirements and complexities of our highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle.Minimum qualifications BE/BS degree in Electrical Engineering with 5+ years of practical experience Strong fundamentals in digital ASIC verification Experience in IP/SS/ SoC level verification of medium to high complexity design Knowledge of one or more of Multimedia design blocks such as Display/ Camera/Video/GFx Familiarity with system level HW and SW Debug techniques and Verification requirements Preferred qualifications MS degree in Electrical Engineering; 4+ years of practical experience Expertise in IP/SS/System level verification flows of one or more of Multimedia design blocks Familiarity with one or more of the bus standard interface protocols for Multimedia designs, such as DisplayPort/ HDMI/ CSI/DSI Exposure to ARM Core debugging techniques would be a plus Strong understanding of AMBA bus protocols A good understanding of the complete verification life cycle (test plan, testbench through coverage closure) Extensive knowledge in multiple testbench structures Exposure to FPGA and emulation platform debugs Proficiency in UVM, C/C++ Experience w/ PSS or higher-level test construction languages is an added advantage Knowledge of assertion-based formal verification is an added advantage Additional Job Description Roles and Responsibilities Define verification architecture, develop test plans and build verification environment Work with design team to understand design intent and bring up verification plans and schedules Verify Subsystems and Full SoC using advanced verification methodologies Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard Debug test cases and report verification result to achieve expected code/functional coverage goal Assist in silicon bring-up, debug and characterization Qualcomm SOC Verification Engineer (Debug) As verification engineer candidate will be responsible to own SoC Debug DV (Crash reset, Trace, debug infra etc) during project work. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams. Skillsets/Requirements : B.E/B.Tech/ M.E/M.Tech in Electronics with 7+ year experience in verification domain. Good understanding of Soc level verification testbench and flows. Working knowledge and design understanding of Debug architecture of a SoC which includes Crash flow, JTAG, Trace, triggers, monitors, Scandump etc. Exposure to Power aware simulations and Gate Level simulations Good understanding of processor based Soc level verification which includes Verilog, System Verilog and UVM based environment. Good understanding of AHB/AXI & ATB-AMBA protocol.

About The Role : ADAS/Autonomous Driving features and relative electronic architectures Experience testing Embedded Software for automotive applications - Body or Propulsion Software/System testing experience. Experience in developing Test Cases, Test Scripts, Test automation, Testing tools and debugging the embedded software using IDEs, debuggers. Experience with Automotive communication protocols (CAN, CAN-FD, Ethernet, SOMEIP, LIN), Experience in SIL, HIL or bench testing with particular focus on dSPACE tools (ControlDesk, MotionDesk, etc.) Demonstrated knowledge about CAN and Automotive Ethernet networks Coding experience in C, C++, Python Experience in Perform validation of ADAS features using automated test suites and system test validation which are aligned with ADAS/AD product requirements Knowledge of network and diagnostic test protocol and tools (eg. INCA, Canalyzer, Canoe) Primary Skills: Body Module (fuel consumption) or Propulsion (gear transmission) Testing, Python scripting, ECU Test tool Test Automation (Ethernet/ CAN), Embedded (Hil), Ethernet SUMIP/UDS, Dspace, Canoe, INCA, Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. About The Role : - Grade Specific Is highly respected, experienced and trusted. Masters all phases of the software development lifecycle and applies innovation and industrialization. Shows a clear dedication and commitment to business objectives and responsibilities and to the group as a whole. Operates with no supervision in highly complex environments and takes responsibility for a substantial aspect of Capgeminis activity. Is able to manage difficult and complex situations calmly and professionally. Considers the bigger picture when making decisions and demonstrates a clear understanding of commercial and negotiating principles in less-easy situations. Focuses on developing long term partnerships with clients. Demonstrates leadership that balances business, technical and people objectives. Plays a significant part in the recruitment and development of people. Skills (competencies) Verbal Communication Python System Testing Test Design Verification and Validation

Must have expertise in ASIC viterification methodologies and ASIC design flow Experience working of SV and UVM methodology and knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR or similar is required, must have executed at-least 2 SoC Verification projects Experience in any of the listed topics: UVM, formal verification, mixed-signal simulations, power-aware simulations Experience in setting up and debugging functional and/or gate-level simulations Experience in translating functional requirements into verification plans Experience in developing verification environment and regression setup. Coverage analysis and closure

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm WLAN HW team in Bangalore is responsible for developing and delivering best in class WLAN/WiFi solutions which are setting benchmark in wireless industry. In this role of WLAN Verification Engineer, you will be verifying the Wireless MAC subsystem. Successful candidate will be required to collaborate with worldwide design, silicon, and architecture teams to achieve all project goals. Hence, we are looking for candidates with strong communication skills . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As a design verification engineer you will work with a fast paced Integrated Wireless Technology (IEEE 802.11) team, with various wireless technologies embedded into an ARM based SOC infrastructure. You will be responsible for developing HW blocks (IP design), conduct High/Mid/Low level Design review and delivery IP to Subsystem team for making complex SoCs. You will be a critical part of the WLAN subsystem, contribute to IP design, sign-off the core to the SOC design team. Skills/Experience: - 3-6 years experience in Digital Design with a leading chipset company - Decent knowledge in Wireless connectivity technologies:IEEE 802.11 a/b/g/n/ac/ax/be - Knowledge in SoC architecture, including CPUs (preferably ARM), communications peripherals, multi-domain clocking, bus & interconnect structures, and power management - Strong fundamentals in one or few of these domain areas - Wireless and Mobile communications, Information theory, Coding theory, Signal processing - Strong knowledge on fixed-point implementation Truncation/Rounding/Saturation concepts - Strong knowledge on Digital communication engines viz., Demodulator, Deinterleaver, Viterbi/Turbo Decoders, Sigma-Delta modulation, Base band filters, FFT etc. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Position: Lead Design Verification Engineer Experience: 6 to 10 yrs Qualification: B.Tech / B.E or M.Tech / M.E in EEE / ECE Job Location: Bangalore Job Type & Shift: Permanent & Day Shift Job Responsibilities: As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Skills & Experience: 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills Interested candidates with suitable profiles please share your latest updated resume to: tanuja.b@creenosolutions.com or connect @ 8309675199 Kindly Note: We are looking for candidates who can join 15 to 30 days notice max.

Position: Design Verification Manager Experience: 12+ yrs (IC + People Management) Qualification: B.Tech / B.E or M.Tech / ME in EEE/ECE Job Location: Bangalore Job Type & Shift: Permanent & Day Shift Major Responsibilities: As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Skills & Qualifications Required: 12+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience with ARM/RISCV Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills Kindly Note: We are looking for candidates who can join 15 to 30 days notice max. For more details please feel free to reach out Karthik @ 7658983115 or You may DM your updated profile to: karthik.b@creenosolutions.com

Role & responsibilities Job description We are seeking a detail-oriented hardware design engineer for design and development activities of our product line (SMPS/Chargers etc). The following would be the main responsibilities: 1. Hands on Experience on, SMPS & Chargers. 2. Knowledge of Power electronics. 3. Hands on Experience in circuit design, simulation, filter design, schematic & Layout, Micorcontroller based designs, UART/RS232/RS485/CAN/ LIN communication, DFMEA. 5. Hands on experience in validation jig designing using arduino. 6. Knowledge of transformers and inductors calculation, Thermal calculations and components selections/design, BOM preparation. 7. Knowledge of power switching topologies. like fkyback, LLC, PFc topologies. 8. Special Preference who has experience in, Inverters design & charger designing etc.. 9. Hands on Experience in Design Verification and Product Validation. 10. Good understanding on EMI/EMC, ESD testing. 11. Resolve issues in mass production of the design and manufacturing assembly line. 12. Go-Getter, Self Learner, Positive Attitude Preferred candidate profile Only Male Candidate, Willing to work in 6 days working setup. Perks and benefits Insurance,Bouns ,PF

We are seeking an experienced Design Verification Engineer to join our team in the semiconductor industry. The ideal candidate will have 3+ years of hands-on experience in verification, including writing UVM tests, debugging, and working with industry-standard simulators. You will be responsible for building and executing comprehensive verification testbenches, ensuring the correctness of complex digital designs, and working with cross-functional teams to improve design quality. Knowledge of Video, Display, GPU, DDR, PCIe, USB, and scripting is an added advantage. Locations: Bangalore, Malaysia, China, Singapore Key Responsibilities: UVM Test Writing & Debugging: Develop, write, and debug UVM-based testbenches for verifying RTL designs. Create comprehensive tests to validate functionality and performance. Simulation & Debugging: Use industry-standard simulators to simulate designs, analyze simulation results, and troubleshoot issues. Debug RTL and testbenches to ensure correctness and high-quality verification. Behavioral Model for Scoreboard: Develop and write behavioral models for scoreboards to monitor and compare expected results against actual results in simulations. UVM Testbench Building: Build and maintain reusable, modular, and scalable UVM testbenches for functional verification of complex digital systems. Client Project Experience: Contribute to at least one client project, working with teams to meet customer specifications and deadlines while ensuring top-quality verification processes. RTL Coding (Bonus): Knowledge of RTL coding is a plus, as it will help in understanding design implementation and improving testbenches. Programming Knowledge (Bonus): Knowledge of C/C++ is advantageous for scripting and enhancing testbenches, improving efficiency and automation. Domain Knowledge (Bonus): Familiarity with Video, Display, GPU, DDR, PCIe, USB protocols and systems, contributing to better design understanding and verification coverage. Scripting Skills: Utilize scripting languages such as Perl, C, and Shell to automate tasks, create verification scripts, and enhance verification flows. Desired Profile of the Candidate: Experience: Minimum 3 years and up to 8 years of experience in digital verification, ideally in the semiconductor industry, with a strong focus on UVM-based verification and debugging. Verification Expertise: Strong experience in writing and maintaining UVM-based testbenches, developing behavioral models, and working with simulators for functional verification. Project Experience: At least one client project experience, ensuring exposure to real-world verification challenges and customer-facing responsibilities. Coding Skills: Knowledge of RTL coding is a plus, providing insight into the implementation of designs and enhancing verification capabilities. Programming Languages: Knowledge of C/C++, scripting with Perl, Shell, or C to automate and enhance verification processes is a strong advantage. Domain Expertise: Experience or knowledge in areas like Video, Display, GPU, DDR, PCIe, and USB is beneficial for handling specialized verification requirements. Required Skills & Qualifications: Technical Skills: Expertise in UVM test writing , simulation, debugging, and building UVM testbenches . Strong understanding of behavioral modeling for scoreboards. Experience with industry-standard simulators for RTL verification. Proficient in scripting using Perl , C , Shell , or similar languages. Optional but Beneficial Skills: Knowledge of RTL coding and C/C++ programming. Experience with Video , Display , GPU , DDR , PCIe , and USB technologies and protocols. Education: Bachelors or Masters degree in Electronics, Electrical Engineering, Computer Engineering, or a related field. Key Competencies: Strong experience in UVM-based verification and debugging. Ability to build and maintain UVM testbenches and work on simulation and behavioral modeling . Familiarity with industry-standard simulators and verification methodologies. Strong problem-solving skills to identify and resolve complex design and verification issues. Effective communication skills to collaborate with cross-functional teams and clients. Ability to work independently as well as part of a team in a fast-paced environment.

About The Role : DEG/IMSG seeks an experienced pre-Si verification engineer for its PCIe IP development organization, a dynamic team with a history of outstanding execution and industry-leading accomplishments. We are looking for an enthusiastic individual with a strong background in all aspects of IP development and a proven capacity for understanding new technologies, to help deliver on our charter as Intel's center of innovation for IO and Accelerator technologies. You will be responsible for, but not limited too. Working with a high performing team to deliver fully functional IPs on Intel's latest process technology to reduce product risk for various enterprise IPs including PCI express and accelerators. Interfacing with architects and senior design/val team members to develop new features. Roles and responsibilities Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches (BFM, Scoreboard, tests) , and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification Qualifications Qualification Candidate should possess a bachelor's degree in electrical, Electronics, Computer Engineering or Computer Science or any related field with 10+ years' experience -OR - a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 8+ years of experience -OR- PhD degree in Electrical, Electronics, Computer Engineering with 5+ years of experience. Mandatory Skills :- SV /UVM, Mirco, test bench , test plan creation , coverage analysis , debugging/problem solving skills . Preferred skills :- BFM development , third party VIP integration , evaluation of VIP's , formal verification skills and c++ Preferred Protocol knowledge on PCIE , Cxl* , Solid verbal/written communication skills.o Effective team player with continuous learning mindset. Be willing to balance multiple tasks. Prior experience in IP development teams would be an added advantage. The candidate must be able to work independently and be self-motivated to identify, innovate upon, architect and deploy Formal Verification solutions. Experience in BFM development. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

This position is within the process diagnostics and control (PDC) group, which deals with advanced imaging together with cutting edge image processing algorithms and design CAD in order to detect, measure and classify nanometer size defects from semiconductor fabrication process steps. Application engineers are supposed to maximize the performance of our new defect metrology products through a deep and thorough understanding of use-cases in close technical collaboration with leading-edge chip manufacturing customers. Build and maintain strong relationships with customers, including regular communication, feedback and follow-up to ensure customer satisfaction and success. Work closely with internal Product teams including R&D, marketing and internal Account stakeholders to ensure alignment, effective communication and customer engagement. At a higher expertise level, they also contribute to product development roadmap through spec definition and performance validation. They also contribute to SW Application Alpha/Beta phase of qualification in-house and at customer site. Desired qualification: Master's / Bachelor's degree in Electrical/Electronics Engineering, Mechanical Engineering, Computer Science Engineering or in a related field. 2 to 5 yrs experience in Semiconductor Design, Design Verification, Fabrication or in related field, with focus on technical support, training and/or product development. Sound fundamentals of high-NA DUV imaging/SEM and light-matter/electron-matter interaction Open to on average 50% travel to leading semiconductor chip manufacturing fabs overseas Lab/fab hands-on experience in semiconductor fabrication with layer-wise detailed knowledge of material, process tech and defectivity Detail oriented with strong analytical, problem solving and communication skills Ability to work in a team, and ability to work independently Qualifications Education: Master's Degree: Electronics Skills: Design Verification, Fabrication Design, Semiconductor Design

About The Role : Do Something Wonderful. Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Come join us -- Who We Are In this role you will be part for the Server SoC Design Validation team, working on next-generation Xeon server product SOCs and IPs. Who You Are Your responsibilities include but are not limited to: Performs functional logic verification and emulation validation of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products. Behavioral traits that we are looking for: Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer. Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks. Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience Related technical experience should be in/with:Silicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Experience on Pre-Si validation on Emulation, preferably Zebu.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Bachelors or Masters from Engineering Background and Preferably from IIT, NIIT or Top ranked Institutes. Minimum Qualifications:Strong coding experience in perl, python (one of the programming languages). Strong in system Verilog 3 + years' experience on AMBA protocols. Strong in computer architecture.Preferred Qualifications:Bringing up coherent protocols from 0 to1. 1-3 years of Experience on Network on Chip verification. 1-3 years of experience developing protocol checkers, bridge checkers, VIP integration, 1-3 Configurable IP verification. Strong background and experience on Coherent Protocols (IDI, CHI). Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

Position Overview: We are hiring an experienced Pavement Engineer to lead the design, execution, and quality control of multi-layer pavement structures for highways , runways , taxiways , and aprons . The role involves managing all pavement layers from the subgrade to the bituminous wearing course , ensuring compliance with technical specifications and international standards. Key Responsibilities: Design and Execution: Develop and oversee the execution of pavement designs, considering all layers from subgrade to bituminous concrete layers in accordance with MoRTH , DGCA , and ICAO standards. Manage and supervise construction activities for the following pavement layers: Subgrade Preparation: Evaluation of soil characteristics, stabilization (if required), and compaction. Granular Sub-Base (GSB): Laying, compaction, and quality testing of the base layer for load distribution. Wet Mix Macadam (WMM): Supervising the laying of WMM layers, ensuring proper compaction and density. Dense Bituminous Macadam (DBM): Monitoring the binder course using VG 30 bitumen for structural integrity. Bituminous Concrete (BC) Wearing Course: Application of VG 40 bitumen for high resistance to rutting and wear. Quality Control and Testing: Approve and verify Job Mix Designs (JMDs) for each pavement layer. Conduct field and laboratory tests for material quality Ensure proper slope correction, drainage facilitation, and surface evenness using specialized equipment like the Big MultiPlex Ski Sensor . Project Management: Coordinate with clients, project managers, subcontractors, and independent engineers for smooth project execution. Oversee equipment operations for subgrade preparation, GSB, WMM, and bituminous layer construction. Monitor project timelines and ensure timely completion of each layer according to specifications and safety standards. Manage material usage, generate progress reports, and document quality assurance results for client submission. Implement corrective actions in case of deviations from design specifications or quality failures. Key Requirements: Bachelors Degree in Civil Engineering (Masters degree preferred). Minimum 6 years of experience in pavement design, execution, and quality assurance for highways or runways. In-depth knowledge of pavement layer specifications and construction materials as per MoRTH , DGCA , and ICAO guidelines. Proficiency in pavement design software (e.g., KENPAVE , MX Road , AutoCAD Civil 3D ). Experience operating and supervising advanced equipment, such as sensor paver finishers and Big MultiPlex Ski Sensors . Strong knowledge of material testing for granular and bituminous materials, including field and laboratory procedures. Excellent leadership, communication, and project management skills. Key Skills: Pavement design for all structural layers (Subgrade, GSB, WMM, DBM, BC) Bituminous and non-bituminous material testing and quality control Project management and scheduling Surface leveling and slope correction using advanced equipment Quality assurance and documentation Regulatory compliance with MoRTH , DGCA , and ICAO standards Technical documentation and report generation Proficiency in AutoCAD , MS Office Suite , and pavement design software Perks and Benefits: Competitive salary (based on experience and qualifications) Accommodation and meals provided at the project site Career advancement opportunities in large-scale infrastructure projects On-the-job technical training and development

About The Role : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Bachelor in Electronics & communication Engineering, Computer Engineering, and/or Computer Science plus 4 to 6 years of relevant work experience, Masters in Electrical Engineering, Computer Engineering, and/or Computer Science plus 3 to 5 years of relevant work experience. Experience owning a testplan and executing to verification closure. 4 plus years of experience in SystemVerilog, OVM/UVM. Knowledge of AMBA protocols (AXI, AHB, APB). Knowledge of PCIe is a plus. Knowledge of power aware verification is a plus. Strong scripting skills. Excellent verbal and written communication skills. Exposure to Formal verification techniques is a plus. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

About The Role : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Candidate should possess a bachelor's degree in electrical, Electronics, Computer Engineering or Computer Science or any related field with 6+ years' experience-OR -a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 4+ years of experienceMandatory Skills :- SV /UVM, Mirco, test bench , test plan creation , coverage analysis , debugging/problem solving skills .Preferred skills :- BFM development , third party VIP integration , evaluation of VIP's , formal verification skills and c++ Preferred Protocol knowledge on PCIE , Cxl ,Solid verbal/written communication skills.o Effective team player with continuous learning mindset.Be willing to balance multiple tasks. Prior experience in IP development teams would be an added advantage.The candidate must be able to work independently and be self-motivated to identify, innovate upon, architect and deploy Formal Verification solutions. Experience in BFM development Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

About The Role : Creates quality emulation collaterals using UVM System Verilog/SystemC and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals for validation readiness. Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-silicon and post-silicon functional and performance validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to presilicon Validation teams for optimizing pre-silicon validation environments, test suites and methodologies for emulation efficiency. Develops and applies automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. Job Experience: Technical experience in verification of RTL-based digital systems with very good understating of various system level flowsExperience leading development of verification architecture based on evolving requirement from IP/SOC customersExperience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog/SystemC based verification techniques.Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environmentsExperience in SW Programming/scripting and debug such as C, C++, Perl, PythonWork experience creating a self-checking emulation/simulation test benchHighly proficient in UVM techniques for verificationHands-on experience of emulation and simulation BFM based verificationGood understanding of architectural design documents(micro-architecture documents, integration documents)Preferably good understanding of emulation/simulation platform with major vendors (Synopsys, cadence )Protocol knowledge :PCIE, CXL, UCIe, CHI, DDR Good understanding of CPU architecture (Intel/AMD/Arm/GPU)Highly proficient with coherent, non-coherent and concurrent traffic validationExperience with emulation based systems such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic VeloceExperience in building emulation based models for large scale designs is a plus Job Responsibilities: Work closely with peers in architecture, design and verification teamsShould be able to review the IP teams requirements, come up with verification plan, test plan, micro-arch, identify scenarios and design intent and develop verification strategies which can ensure defect free IP'sMaintain generic emulation based verification environment and regression setups for various IP'sLeads activities driving the development of various stimulus to support the emulation based verification of various IP'sDevelop and maintain UVM environments for IP interfacesWork in cross-functional teams to deliver bug free features in a timely manner Qualifications QualificationsThis position requires meeting the below minimum qualifications to be initially considered. Preferred qualifications are in addition to the minimum requirements and are considered a major plus.Minimum Qualifications:Must have a Bachelor's degree with 15+ year experience or Master's degree in Electronics and Computer Engineering with relevant experience of at least 10+ years Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.