DESIGNATION: ANALYST DESIGN QUALITY ENGINEER Contract Duration: 12 - 24 Months PRIMARY RESPONSIBILITIES: Ensures that designs meet regulatory requirements, quality standards, and company policies throughout the product lifecycle (FDA 21CFR Part 820 Quality System Regulation, ISO 13485 Regulations, ISO 14971) Review design documentation, specifications, and data to identify potential compliance gaps and quality issues. Responsible for developing and implementing compliance programs, identifying potential issues, and recommending corrective actions to ensure product safety, reliability, and efficacy. Maintain accurate and up-to-date documentation related to compliance activities, including test results, reports, and procedures. Hands-on experience in Design History File compilation / Technical file documentation. Experience in complaint investigation, corrective action and preventive action system, statistical methods, quality risk management and Post Market Surveillance. Possess a strong understanding of design principles, quality control standards, regulatory requirements, and problem-solving methodologies. QUALIFICATION: A graduate in Mechanical or related engineering and with 4-6 years related medical device /combination product design & development experience and product lifecycle management.

Extensive experience in IP/SOC Verification. Proficiency in System Verilog and UVM. Hands-on experience in verifying IP protocols such as PCIe, DDR, USB, Ethernet, CXL, HDMI, MIPI, DSI, CS, GLS, CPU Verification, or other high-speed protocols. Familiarity with scripting languages like Python, Perl, TCL, etc. Experience in assembly language or C is a plus. Ability to develop testbenches from scratch and take ownership of the entire verification process, including subsystem/chip-level coverage. Strong debugging skills. Location: Chennai and Ahmedabad,Bengaluru,Hyderabad,Pune

Division R&D Level / Grade EX Functional Area Design 2WH Vertical: 2 Wheelers 1 Job Title Manager R & D 2 Reporting Functional reporting to : LX 3 Background i) Educational Qualification B Tech (Mech), M Tech (Mech) or equivalent Desirable: B Tech/M Tech from NITs or IITs ii) Experience Minimum: 5 Maximum: 12 iii) Age Limit Minimum: Maximum: 40 Year(s) 4 Job Role & Responsibilities Role: Manager - 2W Vehicle Integration Responsibilities: Project Management / Vehicle Integration for Bajaj 2wh, mainly performance segment Motorcycles: Driving Projects independently from initial Vehicle Layout / concept preparation to final production readiness Passing all Gate Reviews and clearances with all stake holders Identifying and completing relevant benchmarking for the projects, setting weight and cost targets based on benchmark Basic Vehicle Calculations, fixing layout Hard Points, Modularization across different Variants Layouts, estimating project scheduling and making time plans. Specification preparation and finalization. Design Verification and Validation Planning, setting up vehicle level and component level test plans. Concept design preparation based on requirement and sharing with horizontal to complete detail design, layout checking and confirming it meets the targets and release in system. Detail Design Reviews, early detection of potential issues related to Durability, NVH, DFA, DFS, DFMs and Releases after improvements for Proto / Pilot / Production. Meeting target schedules. Responsible for Vehicle Proto build, Pilot and SOP batch built and resolving all DFA, DFS, DFM concerns with relevant teams. Responsible for resolving all internal and external Quality issues. Meeting cost targets, generating VAVE ideas to reduce cost. Responsible for communicating / addressing all issues with external departments like plant/ CD/ service and marketing. Responsible to provide weekly / monthly updates for management reviews Should be able to manage multiple MPLs/ Multiples projects at a time. 5 Competency Requirements Technical/ Functional: Proven capabilities in area of Vehicle Engineering, Vehicle Dynamics, Chassis design, Plastics, starting from initial Vehicle Layout, all the way up to final production releases Deep Technical competency in understanding the 2wh design. Deep knowledge and Proven expertise in Frame design, Plastic component design, Design Verification & Validation Fair knowledge for CAE Calculations, DMU, DFMEA, DFA, DFS. Fair knowledge of complete vehicle sub systems including frame, trims, fuel system, engine mtg, wheel & brakes, electricals. Understanding & good working skills on CAD software s like NX (preferred), catia, Creo and teamcenter. Good knowledge of MS office. Adequate knowledge of prevalent Indian and European Regulations Behavioral Team player. Should have managerial experience of working with engineers and designers of varying skills, experience and age. Positive attitude, eager to take new responsibility new work, passionate engineer who wants to build world class motorcycles. Must be having system-oriented approach to manage multiple projects at a time without delays. Ability to manage complex team ecosystem Senior Engineers, Junior Engineers Diplomas Cross-department conversations and requirements to be handled, must be able to do clear communication with clear targets and work allocation. Should be able to demand and complete work as per schedules Specific expertise required for functional area: Expertise in few Design areas at least (like frame or plastics) Ability to generate new ideas to resolve issues. 6 Likely Sources OEMs - Hero, Harley, M&M, Tata Motors

Hiring Freshers Kickstart Your Career in VLSI At PRSsemicon Technologies, we are shaping the future of semiconductor innovation by building a Global Capability Development Centre. We are looking for fresh graduates passionate about VLSI domains to join our team. Through structured training and hands-on experience, we ensure you gain the technical expertise and industry-relevant skills required to succeed in this dynamic field. Your Journey with Us: Comprehensive Training Gain in-depth knowledge of VLSI design, verification, emulation, DFT, physical design, and analog design based on project needs. Hands-on Experience Work with industry-standard tools and methodologies. Expert Guidance Learn from seasoned professionals and build practical expertise. Live Project Transition Successfully complete training and contribute to real-world chip design projects. What We Look For: Strong fundamentals in Digital Electronics. Eagerness to learn and build competency before taking on project responsibilities. Passion for VLSI design and a commitment to a long-term career in semiconductors. Why Join PRSsemicon? Be part of Indias thriving semiconductor industry. Learn from experienced professionals in a structured training environment. Get hands-on exposure to cutting-edge chip design projects. Headquarter: Chennai Mode: Offline/Online/Hybrid (as per project requirements) Eligibility: B. Tech/M. Tech in ECE, EEE, E & I, VLSI, or related fields Year of passing out: From 2022 and below (2021, 2020.. ) will be considered Apply Now & Shape the Future of VLSI with Us!

Skills: Programming Language : Strong in VHDL along with Working knowledge on Verilog/System-Verilog Preferable Skills: * Use of tools such as Quartus, Vivado, Libero and their IPs * Experience with using any simulator (Modelsim, XSIM, etc.) * Deep understanding of FPGA design flow including RTL design, verification, logic synthesis, timing analysis, floor-planning, ECO, bring-up & lab debug. * Experience with gate-level understanding of RTL and synthesis * Experience with basic lab equipment such as Logic analyzers, scopes, protocol analyzers, etc. * Development experience and board level debugging on Ethernet (1G, 10G) experience is preferable * Experience in DDR3/DDR4 is preferable * Experience in AMBA/AXI is preferable * Good interpersonal and communication skills Vhdl

Areas of Responsibility Circuit design and verification of the CMOS I2C IO and GPIO libraries. Develop I2C IO and GPIO (operation up to 200MHz) architecture to meet the specifications. Develop 3.3V architecture using 1.8V MOS to meet the design & reliability specifications. Optimisation of the design, verification of the functionality, performance, power using Cadence Virtuoso circuit design suite (ADE-XL) Working knowledge of the layout to guide the layout engineers on the implementation of the critical structures for matching, shielding and routing requirements. Strong problem-solving skills, results orientation, attention to detail, and effective communication skills are the key for this position. position Requirement: Experience: 5 10 years of experience in the areas of analog and IO circuit design, with good experience in designing Overvoltage, Failsafe & I2C compatible IO interfaces. Desired Skills : Strong hands on experience in CMOS IO design, programmable driver Impedance control, Impedance matching of transmission line. Solid hands on experience working with Cadence Virtuoso circuit design suite (ADE-XL) Good technical knowledge of power-performance trade-offs. Strong understanding of the impact of device parameter variation on design performance. Basic understanding of IO library views like .lib, IBIS generation Basic understanding of ESD & LU concepts. Independent ownership of circuit blocks. Clear communication and diligent documentation of the work. Good team player in a multi-site work environment Analog Circuit Design

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Roles and Responsibilities o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. o Work closely with design/verification teams within CPU to develop comprehensive test plan. o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. o Verify power intent through use of methodologies like UPF. o Work closely with system architects, software teams and Soc team to validate system use cases. o Work closely with emulation team to enable verification on emulators and FPGA platforms. o Debug and triage failures in simulation, emulation and/or Silicon. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. o BE/BTech degree in CS/EE with 3+ years"™ experience. o Experience in power management verification. o Implementation of assembly and C language embedded firmware. o Experience in C/C++, scripting languages, Verilog/system Verilog. o Strong understanding of power management features in CPUs and CPU based Socs. o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements: o Good Understanding of CPU architectures and CPU micro-architectures. o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture o Experience with advanced verification techniques such as formal and assertions is a plus o Knowledge and verification experience in DFT and structural debug concepts and methodologiesJTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Excellent Design verification domain expertise of min 3 years upto 6 years. Develop test strategy, TB architecture and test plan for new IP"™s/new features Develop strategies for re-useable, scalable and enhance Sub system level verification environment Excellent C/System Verilog/Verilog skills to handle C based TB environment Strong skills in debug, post silicon debug-failure re-creation and root cause analysis Scripting proficiency - PERL, Python, for developing applicable automation AMBA, AXI bus protocols Power intent verification, GLS etc. Capable of communicating effectively with all stakeholders across the globe Capable of seeding a new team for new IPs, able to hire and expand the team in expertise and efficiency Capable of mentoring the team members for their career growth, maintaining diversity in the team, collaborating with other leads and managing multiple parallel projects Take initiatives to enable various ideas for improving efficiencies. Good to have Image Processing, DSI/DP/HDMI Protocols Good knowledge of new methodologies, flows and tools to be incorporated. Formal Verification

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Chennai is looking for a VLSI engineers who is passionate in to work with cross-functional engineering teams . In this position, the engineer will be involved in all stages of the design and development cycles Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills 2-4 yrs experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 2 - 4 yrs of experience is preferred

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. About The Role Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications Master's/Bachelor"™s degree in Electrical Engineering, Computer Engineering, or related field. 8+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: s verification engineer candidate will be responsible to manage UFS/Ethernet/PCIe/high speed IP verification at one or more SoC (System On Chip) during project work. Responsibilities Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) . Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronics with 5+ year experience in verification domain. Prior work experience on IP level or Soc level. Prior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable. Good understanding of processor based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment. Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs). Hands on experience in UVM. C/C++ ,System Verilog verification language. Good understanding of AXI-AMBA protocol variants. Can work with scripting language (shell, Makefile, Perl ) Strong understanding of design concepts and ASIC flow. Good problem solving , analytical and debugging skill is must. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Design verification SOC Verification UVM, OVM Verilog, System Verilog Test Bench, Test cases

Responsibility 4 management of Design activities including RFQ'S Design freeze/Release, DFMEA,PPAP, Design Verification/Product Validation testing & CAE.Present design, cost, changes.Liaise closely with all depments 2 fully u/stand design requirement Required Candidate profile He must know Catia & from SEAT background.Conceptualize new designs & design revisions.Improve reliability performance 2 reduce warrantable issues in the field.Deal with parts suppliers, Prototyping

"> Search Jobs Find Jobs For Where Search Jobs R&D Engineering, Sr Engineer Bengaluru, Karnataka, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 10232 Date posted 03/24/2025 Share this job Email LinkedIn X Facebook We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an enthusiastic and skilled Python Developer with a knack for building innovative software solutions. You have a strong background in Python app development and basic knowledge of Django. While not mandatory, familiarity with React, DB Architecture and management, and Linux would be advantageous. You are committed to delivering high-quality, efficient applications and thrive in collaborative environments. With 2-3 years of experience in software development, you are adept at translating requirements into robust, scalable, and secure technical solutions. Your passion for technology and problem-solvin g skills makes you a valuable team player who is eager to contribute to Synopsys mission of driving technological innovation. What You ll Be Doing: Designing, developing, and maintaining scalable, high-performan ce applications. Working closely with cross-function al teams to understand requirements and translate them into technical solutions. Implementing secure coding practices and ensuring application security. Participating in code reviews and providing constructive feedback to peers. Identifying and fixing performance bottlenecks and bugs. Staying updated with the latest industry trends and technologies to ensure our applications remain cutting-edge. The Impact You Will Have: Contributing to the development of high-performan ce applications that drive Synopsys technological advancements. Enhancing the user experience through reliable and efficient software solutions. Improving application security and performance, ensuring robust and secure products for our clients. Collaborating with diverse teams to foster innovation and creativity within the organization. Driving continuous improvement in our development processes and practices. Supporting Synopsys mission to lead in chip design, verification, and IP integration. What You ll Need: Strong proficiency in Python programming. Basic knowledge of Django framework. Experience with React and DB Architecture and management (preferred). Familiarity with Linux operating systems (preferred). 2-3 years of experience in software development. Who You Are: Detail-oriente d and committed to delivering high-quality applications. Excellent problem-solvin g skills and a proactive attitude. Strong communication skills and the ability to collaborate effectively with cross-function al teams. Adaptable and eager to learn new technologies and techniques. Passionate about technology and innovation. The Team You ll Be A Part Of: You will be part of a dynamic and innovative team at Synopsys India, focused on developing cutting-edge software solutions. Our team values collaboration, creativity, and a commitment to excellence. We work closely with various departments to ensure our products meet the highest standards of quality and performance. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

Working closely with a world-class R&D team, you ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM). Working closely with customers, you will bring the detailed requirements into the factory to enable R&D for a strong, robust, and successful product development. Working closely with product development team, you will validate and end-to-end solution both internally (before shipment) as well as in customer environment. Driving the deployment and smooth execution of SLM solutions into customers projects. Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations. The Impact You Will Have: Enhancing Synopsys Silicon Lifecycle Management (SLM) IP portfolio and end-to-end solution. Driving the adoption of Synopsys SLM solutions at premier customer base worlwide. Influencing the development of next-generation SLM IPs and solutions. What You ll Need: BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field. 4+ years of hands-on experience with SoC-level functional verification or Design-for-Test (DFT) or both. Good knowledge of AXI, APB Background in verification, with at least sub-system level verification Debugging abilities to identify issues in functional verification. Knowledge of DMA, ideally should have verified a sub-system with DMA Knowledge of High-speed IO sub-systems like PCIe and USB A thorough understanding of memory mapping concepts is essential. End to end knowledge of how transactions/data flow between the HSIO interface to/from memory Knowledge and experience with Memory BIST/DFT/ATE/SLT/any other test solutions Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions Customer facing experience is a plus - educating/guiding customer on technical details of a solution Good to have: Hands-on debug experience of silicon is a plus Some programming experience to write/debug simple drivers in C Detailed knowledge of the PCIe and USB protocols Architecture/micro-architecture experience Working with FPGAs

You are a seasoned professional with a passion for analog design and a knack for solving complex problems With a strong foundation in CMOS processes and deep submicron technologies, you bring a wealth of knowledge and experience to the table You thrive in a collaborative environment, where your excellent communication skills enable seamless interactions with internal development teams You are adept at executing circuit design tasks with precision, ensuring the highest product quality and efficiency Your familiarity with ASIC design flow and JEDEC standards for DDR interfaces sets you apart, and you are always eager to learn and adapt to new challenges Your technical acumen, combined with your dedication and innovative mindset, makes you an ideal fit for our team What You ll Be Doing: - Ownership of complete physical implementation at block level & chip level. Responsible for delivering timing clean blocks/chip level that meet design targets. - DRC, LVS & IR closure. Evaluates all aspects of the physical design flow from place and route, timing, PV & IR and is able to setup these flows. - Experience in all chip level tasks (P&R, STA, PV, IR) . Work closely with the frontend design team to resolve design issues . The Impact You Will Have: * Enhancing the performance and efficiency of our silicon IP portfolio. * Contributing to the rapid integration of advanced capabilities into SoCs. * Reducing the time-to-market and risk for our customers products. * Driving innovation in analog design and setting new industry standards. * Strengthening Synopsys position as a leader in chip design and verification. * Empowering the development of high-performance, differentiated products. What You ll Need: - Candidates with MSEE/BSEE with 5+ years of related experience. Possesses in depth understanding of specialization area plus working knowledge of one other related area. - Resolves issues in creative ways. - Exercises judgement in selecting methods and techniques to obtain solutions. - Executes project responsibilities from start to completion. - Contributes to moderately complex aspects of a project. - Determines and develops recommendations to solutions. - Works on team-driven or task-oriented projects. - May guide more junior peers with aspects of their job. - Networks with senior internal and external personnel in own area of expertise. - Strong knowledge on scripting using tcl, perl . Who You Are: * A collaborative team player with a proactive approach. * Detail-oriented with a commitment to quality and efficiency. * Innovative and adaptable, always seeking to learn and grow. * Effective communicator, able to convey technical information clearly. * Problem-solver with strong analytical skills.

"> Search Jobs Find Jobs For * Designing and developing DDR I/O circuits to meet performance and power specifications. * Collaborating with cross-functional teams to integrate analog circuitry into SoCs. * Executing circuit design tasks with a focus on product quality and efficiency. * Conducting layout reviews and ensuring adherence to design methodologies. * Participating in design reviews and providing technical insights. * Staying updated with the latest advancements in CMOS processes and deep submicron technologies. The Impact You Will Have: * Enhancing the performance and efficiency of our silicon IP portfolio. * Contributing to the rapid integration of advanced capabilities into SoCs. * Reducing the time-to-market and risk for our customers products. * Driving innovation in analog design and setting new industry standards. * Strengthening Synopsys position as a leader in chip design and verification. * Empowering the development of high-performance, differentiated products. What You ll Need: * BTech/MTech in Electrical Engineering or a related field. * 4+ years of experience in CMOS circuit design and layout methodology. * Strong knowledge of deep submicron process technologies. * Familiarity with ASIC design flow and JEDEC standards for DDR interfaces. * Excellent written and verbal communication skills. Who You Are: * A collaborative team player with a proactive approach. * Detail-oriented with a commitment to quality and efficiency. * Innovative and adaptable, always seeking to learn and grow. * Effective communicator, able to convey technical information clearly. * Problem-solver with strong analytical skills.

Experience: 6+ years of experience in pre-silicon RTL Verification /IP Verification / SOC verification, Strong knowledge of System Verilog and working knowledge of recent verification methodologie Required Candidate profile Notice Period: 0- 60 days Education: BE/ B.Tech/ Master degree in Electrical Engineering or Computer Science

Skills : Functional specifications of the IPs, subsystems and SOC, Reviewing and Revising, System Verilog, UVM, Performing RTL simulations using Synopsys and Cadence simulators, Performing UPF

As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Basic qualifications Bachelor s/ Master s degree or higher in EEE/ECE 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skill

As an embedded test engineer, you will focus primarily on ensuring the hardware and software/firmware quality of our embedded systems. Your responsibilities will include, but not limited to: Defining test methodology for ensuring the quality of embedded firmware and hardware Creating/defining the necessary tools and test plans for conducting firmware testing and hardware design verification Generating test cases for both hardware design verification and firmware testing Working closely with firmware, hardware and requirements engineers to ensure optimal test coverage Working closely with test technicians executing test cases to ensure they have the corrects tools and understanding of the test cases Developing new processes and tools to speed the testing process (e.g. auto testing) Creating production functional test specifications for both subassemblies and final assembly Performing root cause analysis to enhance the on-going quality of products Actively participating in multidisciplinary project teams through all phases of product development to ensure successful execution of innovative and best-in-class designs Requirements: B.E. in Electrical Engineering 6+ years test experience (hardware design verification, embedded firmware test and production electrical test) Knowledge of Blue Tooth Low Energy specification, RF tests and test equipment Excellent written and verbal skills Strong analytical and problem-solving skills Detail oriented Working knowledge of test equipment (e.g. scopes, data acquisition systems, communication analyzer, spectrum analyzer, etc) Desired Skills/Experience C, C-sharp or a scripting language suitable for automating firmware tests RF Phy testing experience (BLE), both for SIG compliance and production test IMU test experience Regulatory/safety knowledge (CEC, CE, UL, CEA, etc.) Automated test experience