407 Design Verification Jobs - Page 6

Grade G - Office/ CoreResponsible for managing a team and delivering Engineering Leadership through provision of technical expertise to projects or operations, including maintenance, inspection and turnaround, recommendation of technical solutions and management of engineering studies and risk assessments, driving integrated and pragmatic solutions, whilst assisting in implementing engineering technical practices for the business to advance the technical integrity of assets. Entity: Production & Operations Engineering Group Job Description: About us bp Technical Solutions India (TSI) centre in Pune, aims to build on bp s existing engineering and technical strengths to deliver high quality services to its hydrocarbons and new energy businesses worldwide. TSI brings together diverse engineering capability to provide technical services across a range of areas including engineering, maintenance, optimization, data processes, projects and subsurface, to deliver safe, affordable, and lower emission energy, while continuously innovating how we work. About the role About us At bp we deliver the energy the world needs today and for tomorrow. Developing new projects to support the bp strategy is critical to delivery of value to shareholders and thoughtfully support the energy transition. Projects include new energies such as hydrogen and biofuels as well as hydrocarbon developments critical to keep the world moving and enable the transition. Projects in bp is a dynamic, challenging and worldwide organisation taking on the most exciting projects ranging in size from $100m to multi $billions. We strive to do these even more safely, efficiently and predictably. Our projects team is now building worldclass capability in India as a new hub of Production and Operations (P&O) Projects India supporting both local and international projects. Role Synopsis: The Engineering Manager will join the Projects India organisation in the engineering and quality team to oversee and lead the engineering team, providing oversight, judgment and support to Projects. The role will lead engineering activity, including design, verification and interfaces to the project management and procurement. The role is based at the Pune office but will require significant contractor facing work at major engineering contractor office locations in both India and possibly ex-India. What you will deliver Deliver engineering safe, cost effective and competitive project engineering designs by leading a multidiscipline engineering team deployed from discipline leaders. Establish and support the engineering processes to deliver engineering. Lead, oversee and performance manage the engineering contractors day to day activities to deliver the agreed plans, budgets and quality. Monitor the preparation, review and approval of procurement procedures, approved vendor lists, purchase requisitions, invitations to tender, etc. within the team s scope as required. Work with the Health, Safety, Security, and Environment departments to support the project requirements, design basis and commitments. Accountability for the HSSE performance of the team s engineering scopes. Monitor and feed into the performance of project staff, agency and bp and feed into their performance and career development. Interface with people all levels of project including engagement with project leadership teams, both in India and ex-India. Focal point for some third parties. Ensure project meets engineering standards and that design proceeds compliant with BP s Operating Management System (OMS), Projects development Common Process (PdCP), and Engineering Technical Practices through all stages of the project Lead the engineering team to ensure that support of construction, commissioning and operations readiness as part of overall What you will need to be successful Must have educational qualifications: Bachelor s or Master s Degree in relevant Engineering subject (including Chemical, Process, Electrical, Mechanical) Preferred education/certifications: Chartered Engineer or Registered Professional Engineer Minimum years of relevant experience: 15+ yrs in oil and gas / petrochemical / refining / chemical or equivalent, with minimum five (5) years experience of leading multidiscipline Engineering work in major capital projects and 10 years in major capital projects Must have experiences/skills (To be hired with): Major Project experience leading an engineering team working in Front End Engineering Design (FEED), Detailed Design stages of a project. Leading an engineering team, development of junior and senior staff, resource deployment and performance management Demonstrable experience of undertaking multi-discipline decision making in a key engineering role. Understanding of technical and process safety risks Experience managing third party engineering design contractors. Experience on fabrication and construction activities supporting engineering Proactive, performance biased skills and demonstrable track record of delivery. Working knowledge of international industry codes and standards. Experience of set-up and leading major project processes and technical engineering processes (including technical queries, management of change, deviations, action tracking) Ability to communicate effectively with all levels of the project team, contractors and project leadership. Experience of leading scopes of work, tendering, awarding, kicking off and running engineering contracts Developing and building networks and respects the contribution of others Good to have experiences/skills (Can be trained for - learning/on-the-job): Experience of working with major package and equipment suppliers. Experience of concept engineering Leading engineering in different contracting models (lump sum; lump sum conversion). Experience as project or package manager on major project Self-motivated with a willingness to learn from others and work with minimum direction % travel requirements Up to 50% Why join bp At bp, we support our people to learn and grow in a diverse and exciting environment. We believe that our team is strengthened by diversity. We are committed to fostering an inclusive environment in which everyone is respected and treated fairly. There are many aspects of our employees lives that are significant, so we offer benefits to enable your work to fit with your life. These benefits can include flexible working options, a generous paid parental leave policy, and excellent retirement benefits, among others! We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation! Travel Requirement Up to 50% travel should be expected with this role Relocation Assistance: This role is eligible for relocation within country Remote Type: This position is not available for remote working Skills: Asking for Feedback, Asking for Feedback, Authentic Leadership, Capital Projects, Coaching, Creating a high performing team, Delegation, Design, Design Verification, Empowering Others, Engineering Codes, Standards and Practices, Engineering in Projects, Front-End Engineering, Giving Feedback, Goal Setting, HSSE, Inclusive Leadership, Lead Engineering, Leading through ambiguity, Leading through Change, Long Term Planning, Major Capital Projects, Major Projects, Managing Performance, Mentoring {+ 11 more}

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 1 position6+y, 1 position4+y Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash.. Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Mandatory Skills: VLSI Physical Verification. Experience: 5-8 Years.

Job description Design Verification Engineer (4 to 15 Years) SoC/IP Verification Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune] Experience: 4 to 15 Years Openings: 4 Positions Preferred - Immediate to 45 Days (Notice Period) ACL Digital is hiring experienced Design Verification Engineers to work on leading-edge processor-based SoCs and IPs. Strong understanding of design verification methodologies (UVM, SV, etc.) Experience with industry-standard protocols (AXI, DDR, PCIe, etc.) Familiarity with ASIC and SoC design flows. Proficiency in scripting languages (Python, Perl) Experience with simulation tools and debuggers. Strong problem-solving and analytical skills Communication and collaboration skills to work effectively with cross-functional teams Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: AMBA, AXI, PCIE, USB, MIPI

Must Have: SV/UVM Test Bentch Development Any Protocols: (PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM) • 8+ years of hands-on DV experience in System Verilog/UVM. •Must be able to own and drive the verification of a block / subsystem or a SOC. •Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. •Must have extensive experience in verification of one or more of the following: •PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM • ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages • Power Aware Simulations using UPF

SE NIOR SILICON DESIGN ENGINEER Role: The ideal candidate is a person with extenstive experience in applying formal verification methods to complex IPs for cpu, gpu and high speed protocols. Responsibilities: Complete ownership and execution of formal verification of cache controllers, computational IPs, floating point units, etc In this role, he/she would be responsible for formal verification of GPU Design by meeting the demands of the constantly evolving project schedule. The successful candidate will be a member of the GFX team. He/she will demonstrate passion towards design, design verification, be a teammate, a problem solver with independence, creativity, and interpersonal skills. Complete ownership and execution of formal verification of cache controllers, computational IPs, floating point units, etc. PREFERRED EXPERIENCE: Vast and deep experience of formal verification methods Domain knowledge in cpu, gpu, serial protocols Must be able to do compexity reduction, bug hunting or similar methods ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1

Job Title Required Qualifications System Verilog, UVM, C Scripting languages (Python, Tcl, Perl) Understanding of bus protocols (AXI, AHB, APB, etc.) Proven written and verbal technical communication skills Ability to collaborate in a team environment Excellent analytical and problem-solving skills. Preferred Qualifications From-scratch development of IP or SoC testbenches Familiarity with RISC-V architecture, Functional Safety Standards (ISO 26262) Background with power-ware (UPF) and gate-level simulations (GLS) Ownership of complete verification cycle (verification planning -> coverage closure) in a project Use of formal verification, particularly connectivity, to confirm SoC connectivity requirements Knowledge of UVM Register Abstraction Layer (RAL) and integration of 3rd party VIPs Experience 4-5 years

Design Verification Engineer (Senior Level - 5+ years experience) Company: HCL Tech Job Summary: We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies. Responsibilities: Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification) Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team Champion best practices for verification code quality and participate in code reviews Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies Provide technical leadership and contribute to the overall verification roadmap for the team Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred) Minimum of 5+ years of experience in Design Verification for complex ASICs and SoCs Proven track record of successfully leading and executing verification projects In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages) Excellent leadership, communication, collaboration, and problem-solving skills Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines Benefits: Competitive salary and benefits package commensurate with experience and expertise Opportunity to lead and influence the verification of cutting-edge technologies Dynamic and challenging work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions

Dear Candidate, We are hiring for Top MNC!! Location: Pune Work Mode: Hybrid-General Shift Contract: 1 Year Required Skills As a member of the Design Verification [Pre-Silicon DV] Team for NXP WCS/SCE BU. You will be responsible for verification of various IPs and/or SoC. Candidate must be self-motivated and capable of working independently or as part of a team. You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have excellent knowledge of computer architecture and design verification fundamentals Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies Must have experience in developing complex test bench in System Verilog using OVM/UVM methodology Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol Experience in Low Power Simulation/UPF setup, debug low power simulation failures. Exposure to scripting languages like Perl, Unix shell or similar languages Good to have some experience with assembly language programming required Excellent written and oral communication skills necessary. If interested, please share your updated cv to arthie.m@orcapod.work

Join our Sustaining Project Team as a Design Quality Engineer. Handle DHF, risk management, V&V, doc control, and ensure compliance with quality systems & regulatory standards. Experience with PLCP, FMEA, and CAPA is preferred. Required Candidate profile This role is strictly focused on Design Quality Engineering. It does not include Regulatory Affairs or Post-Market Surveillance (PMS) responsibilities.

Bachelor's degree in Electrical Engineering, Computer Science or equivalent practical experience. 4 years of experience with Design Verification. Experience with System Verilog and Verification techniques. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science, or a related field. Experience creating/using verification components and environments in methodology (e.g., VMM, OVM, UVM). Experience with scripting languages like Perl or Python. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design verification leads and design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM and/or formally verify designs with SVA and industry leading formal tools. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with Power Management. 4 years of experience with SystemVerilog, Design Verification Test, Universal Verification Methodology. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with Interconnect Protocols (eg. AHB, AXI, ACE, CHI, CCIX, CXL). Experience in low-power design verification. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use. Develop cross language tools and verification methodologies. Create and enhance constrained-random verification environments using SystemVerilog and UVM.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, ComputerScience, a related field, or equivalent practical experience. 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases,and test environments. Preferred qualifications: Master s degree in Electrical Engineering, Computer Science, or equivalent practical experience. Experience with low power, debug, Gate Level Simulation (GLS), formal verification. Experience in driving cross functional teams for quality tape-outs Experience leading design verification of IPs, successfully delivered to many SoCs. Experience in driving or owning Sub system level verification and navigating the dependencies with Stakeholders. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan the verification of digital design blocks at Sub System level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SVA and industry leading formal tools. Debug tests with design engineers to deliver functionally correct design blocks. Participate with architecture, design teams, Sival and Software (SW) teams in defining the overall verification strategy of our SoCs. Be the primary point of contact for functional verification of the IP for cross-functional teams.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases, and test environments. Preferred qualifications: Master s degree in Electrical Engineering, Computer Science, or equivalent practical experience. Experience in one or more of the following; high speed controller and physical layer for peripheral component interconnect express, display port, universal serial bus, universal flash storage or low speed IOs such as improved inter-integrated circuit, serial peripheral interface or universal asynchronous receiver transmitter, etc. Experience with Interconnect Protocols (Advanced eXtensible Interface, AXI Coherency Extensions, Coherent Hub Interface, Cache Coherent Interconnect for Accelerators, Compute Express Link). Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan and execute the verification of high speed Inputs/Outputs (IOs) ( PCIe, display port, universal serial bus or universal flash storage ) or low speed IOs (improved inter-integrated circuit, serial peripheral interface or universal asynchronous receiver transmitter), IP/subsystem functional verification, power controller and chips pervasive IP. Create and enhance constrained-random verification environments using SystemVerilog and UVM or other industry-standard methodologies. Create and maintain verification environments using SystemVerilog, Universal Verification Methodology (UVM), and define and implement testbench components, such as drivers, monitors, scoreboards, and checkers. Develop cross language tools and verification methodologies. Identify and write all types of coverage measures for stimulus and corner-cases.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with digital logic design, computer architecture, and circuit theory. Experience in scripting language (e.g., Python, Perl) or a hardware description language (e.g., Verilog, VHDL). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in low-power design verification. Experience developing and maintaining verification testbenches, test cases, and test environments. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.

Minimum qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test including silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. Experience with ATPG, Low Value (LV), Built-in self test (BIST) or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications: Experience with a programming language like Perl with Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC) and DFT timing and Static Timing Analysis (STA). Knowledge of performance design DFT techniques. Knowledge of the end to end flows in Design, Verification, DFT and Partner Domains (PD). Ability to scale DFT. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Work on a team of Design for testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, Static Timing Analysis (STA) checks. Write a Pattern delivery using Automatic Test Pattern Generation (ATPG). Work with Silicon bring-up. Work on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug and deliver debug patterns. Perform Silicon data analysis.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: GPU Design and micro-Architect who will work across functions like GPU architecture and Systems in design and micro-architecture of the next generation GPU features. Work very closely with Architecture teams to come up with micro-architecture and hardware specification for features Design and RTL ownership Work very closely with Design Verification teams to review test plans and sign off the validation of all design features across products Work closely with physical design teams to achieve the right power, performance and area metrics for the GPU blocks Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

We are hiring a strong Design Verification (DV) engineer. This opening is with our CPU Design Verification team. This role is for you if you are curious about Computer organisation and design, and possess strong digital design fundamentals. This role is with a Hardware design and verification team that develops and builds chips enabling the AI revolution. What you will be doing: You will own and develop verification components, such as checkers, models, coverage, and stimulus. You will work closely with the Architecture, RTL, and Formal Verification teams to design and verify the microarchitecture. You will propose methodology, tests and frameworks to ensure bug-free RTL. You will participate in Design specification reviews, architecture reviews, and reviews of other unit test plans. Build DV code and Algorithms that are of high quality, with excellent time and space complexity, that scale well to higher testbenches. You will actively work on understanding the ARM architecture and coherency protocols, such as CHI. You will learn the microarchitectures of the interconnect, cache, ordering, and memory units in the system. This role will enable you to develop expertise in CPU load/store, MMU, caching, coherency/consistency, fabric, and related areas. You will design and verify the next generation of NVIDIA CPUs and SoCs! What we need to see: BS or MS in Electronics Engineering with a minimum of 3+ years of proven experience Knowledge in Design Verification Methodologies SV/UVM verification languages and methodologies. Strong problem solving - more specifically, DV code like stimulus, models, constraints, coverage Prior experience in Testbench architecture and Verification components A strong understanding of CPU architecture and microarchitecture Way to stand out from the crowd: Understanding CPU Architecture concepts related to load/store, caching, coherency, consistency and ordering Strong Python and other software methodologies for scripting and build automation Experience in handling EDA tools from Synopsys or Cadence With competitive salaries and a generous benefits package, we are widely considered as one of the technology world s most desirable employers. We have some of the most dedicated and experienced professionals in the world working for us, and, due to unprecedented growth, our elite engineering teams are expanding rapidly. If youre a creative and autonomous engineer with a real passion for technology, we want to hear from you! We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, colour, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

Overview We are looking for a highly motivated and detail-oriented Advanced Vehicle Architecture Engineer with strong experience in vehicle ergonomics and DVP execution . In this role, you will be responsible for defining and validating occupant packaging and human factors in support of the vehicles overall architecture. You will lead ergonomic analysis throughout the development cycle to ensure occupant comfort, accessibility, visibility, and regulatory compliance. Responsibilities Develop and maintain vehicle-level ergonomic targets for driver and occupant packaging based on customer usage, benchmark data, and regulatory requirements. Perform and manage Ergonomics DVP (Design Verification Plan) for occupant positions, ingress/egress, reachability, visibility, comfort, and usability. Support and lead the digital and physical assessment of occupant packaging using virtual tools (RAMSIS, CATIA, Siemens Jack, or equivalent) and physical bucks. Create and manage 3D human models to assess posture, clearance, and range of motion across different population percentiles. Collaborate with teams including Interior Engineering, HMI, Safety, Studio Design, Body, and Chassis to ensure that ergonomic requirements are met. Ensure compliance with FMVSS, ECE, SAE, ISO, and OEM-specific ergonomic standards . Support interface points definition such as seating positions, pedal and steering locations, H-point strategy, vision angles, and control layouts. Document and communicate ergonomic performance results, risks, and mitigation plans across vehicle development phases. Contribute to benchmarking and user studies to drive best-in-class occupant experiences. Present ergonomic assessments and DVP status at design reviews, gateway meetings , and management reviews. Qualifications Bachelors degree in Mechanical Engineering, Industrial Engineering, Human Factors, Ergonomics, or a related field . 5 to 10 years of experience in automotive vehicle architecture or ergonomics engineering. Proficient in ergonomic simulation tools (e.g., RAMSIS, Jack, CATIA, Siemens NX). Strong understanding of human factors engineering, occupant packaging, and design validation plans . Experience with vehicle packaging, occupant positioning strategies, and regulatory requirements . Knowledge of Design for Usability , anthropometric data application, and posture analysis. Excellent communication, cross-functional collaboration, and problem-solving skills. Essential skills Masters degree in Human Factors, Ergonomics, or Automotive Engineering . Experience working in vehicle development phases from concept to production. Background in interior systems, controls layout, HMI , or visibility studies. Familiarity with global ergonomic regulations and testing standards . Experience Minimum 5 to 10 years of working experience.

Position: Design Verification Engineer Work Location: Pune, India (Hybrid) Contract Duration: 10 Months Experience: 7+ Years Job Description: 7+ years of design verification experience. MS (or higher) in EE/EC/ECC Engineering. Strong background in Pre-Silicon DV. Experience in verification of IPs and/or SoCs. Must have strong System Verilog and UVM/OVM experience. Hands-on experience with: AMBA protocols PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC Good understanding of computer architecture and verification fundamentals. Experience in low-power simulation, UPF setup, and debug. Scripting skills: Perl, Unix Shell, etc. Exposure to assembly/C language diagnostics and assertion coverage. Excellent communication skills.

Urgent Opening for Canvendor! Hiring: Design Verification Engineer (5+ Years Experience) | Bangalore, Hyderabad, Pune | Immediate Joiners Preferred Location: Bangalore, Hyderabad, Pune, India Experience: 5+ Years Notice period: Immediate to 30days Skills Highlighted: System Verilog, Verilog, UVM, AMBA, SOC, IP / ARM Cortex Key Requirements(IP Verification): Extensive experience in executing IP verification or subsystem verification of complex blocks or SOC verification. Excellent in System Verilog (SV), Universal Verification Methodology (UVM), test bench component development, assertions, testbenches, test plans, and coverage. Strong experience in verifying Fabric/NOC/Interconnect blocks. Knowledge of protocols such as AMBA suite (AXI/ACE), PCIe, CXL, interrupt handling, and power management. Experience or knowledge of coherent traffic verification is a plus. Key Requirements(ARM): Strong experience in ARM based SOC and ARM based SS level Design verification Must have worked on ARM based SOC viz Cortex A or M series based SOC Experience in Multi-processor based ARM cpu is plus Coresight Debug knowledge coresight is plus. Strong debug skills with AXI/AHB/APB, memory, and NoC components. Strong work experience in AMBA AXI/AHB protocol based NOC , Strong skills/Proficiency in SystemVerilog, UVM Strong work experience (Advanced skills ) in SV-UVM and/or C based verification. Working knowledge in TB/Checker/SB development is plus. Must possess strong SV/UVM debugging Proficiency in C/C++ modelling. Work Experience or Strong knowledge in Memory SS verification - LPDDR5/LPDDR4/DDR protocols or HBM is plus Work experience in PCIe/CXL and other similar complex protocol like Ethernet is plus If interested kindly share your updated CV to irfanai@canvendor.com Please reach out to this number for more details: +91 95855 44407 (message only)

About the Role : Looking for Cybersecurity Test Engineer who will be working closely with Hardware, Software and Systems engineering teams to deliver the next generation of Automotive SOC's. Ideal candidate is someone who has strong knowledge and hands on experience with Cybersecurity ISO 21434 standards. He/she should be able to Validate Cybersecurity features for Automotive SOC's and its applications. Responsibilities : - Perform penetration testing of SoC Automotive products. - Establish the Security goals and requirements. - Verification strategies in compliance with ISO 21434. - Develop test specifications, test cases, and test plans for security vulnerability testing. - Scan vulnerabilities with regards to CVSS levels and patch fixing from NIST database. - Perform code-level fuzz testing using open source tools. - Support documentation of test results and collaborate with the development team. - Participate in automating test process within CI/CD environments. - Setup and maintain traceability in compliance with Automotive SPICE requirements. - Experience in tools like OpenVAS, Nmap , wireshark, penetration testing for embedded systems. - Experience in Automotive domain is a must. - Practical experience performing TARA, security concepts and other Cybersecurity Artefacts mentioned in IS021434.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Excellent Design verification domain expertise. Develop test strategy, TB architecture and test plan for new IP’s/new features Develop strategies for re-useable, scalable and enhance Sub system level verification environment Excellent C/System Verilog/Verilog skills to handle C based TB environment Strong skills in debug, post silicon debug-failure re-creation and root cause analysis Scripting proficiency - PERL, Python, for developing applicable automation AMBA, AXI bus protocols Power intent verification, GLS etc. Capable of communicating effectively with all stakeholders across the globe Capable of seeding a new team for new IPs, able to hire and expand the team in expertise and efficiency Capable of mentoring the team members for their career growth, maintaining diversity in the team, collaborating with other leads and managing multiple parallel projects Take initiatives to enable various ideas for improving efficiencies. Good to have: Image Processing, DSI/DP/HDMI Protocols Good knowledge of new methodologies, flows and tools to be incorporated. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Senior/Lead ASIC Verification Engineers with an experience of minimum 5+ yrs Very strong experience with Verilog, System Verilog and UVM Working experience on development of Verification IP of layered protocol High Speed peripheral Interface protocol PCIe Gen4+ onwards, PCIe Experience is a must Strong knowledge on UVM RAL and common register interfaces such as APB, AHB, AXI (ARM), RAM. Working experience on scripting and automation Strong Past experience of developing verification plan from scratch and testbench development using the detailed Specification and TestPlan from the scratch Strong base knowledge on digital design, blocks/components Strong debugging skills and Good knowledge of assertions and functional coverage coding and closure. Good knowledge on code coverage analysis and closure. Good knowledge of any scripting language Strong documentation and presentation skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform its potential into world-changing technologies and products. In the role of GPU Functional Verification Engineer , your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools – working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver Experience Minimum 3 years of Design verification experience Senior positions will be offered to candidates with suitable years of experience and proven expertise matching the profiles listed above Education BE/ME/M.Sc. in Electrical, Electronics, VLSI, Microelectronics, or equivalent courses from reputed universities Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR. The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools – both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug