Design Verification Engineer

Proxelera

5 - 10 years

35 - 70 Lacs

hyderabad bengaluru

Posted:5 hours ago| Platform:

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Skills Required

design verification uvm asic verification system verilog sv usb soc verification pcie verification asic axi amba verilog ethernet ahb functional verification ip verification

Work Mode

Work from Office

Job Type

Full Time

Job Description

We are seeking Design Verification Engineers with 515 years of experience in SystemVerilog, UVM, and SoC/IP-level verification. The role involves building scalable verification environments, driving coverage closure, debugging complex issues, and ensuring robust design quality.

Key Responsibilities & Requirements:

Strong experience in ASIC/IP/SoC design verification (block/IP/SoC level).
Expertise in SystemVerilog, UVM, testbench architecture, and reusable verification components.
Ability to create and execute detailed verification plans.
Skilled in constrained-random verification, functional coverage, assertions, and scoreboarding.
Solid knowledge of AMBA protocols (AXI, AHB, APB).
Proficiency with simulation tools (VCS, Questa, XSIM, etc.) and debug tools (Verdi, DVE).
Strong background in testcase development, coverage closure, and issue debugging.
Experience with assertion-based and formal verification techniques.
Hands-on in developing block-level and SoC-level verification environments.
Scripting skills in Python, Perl, or TCL for automation.

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