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Qualcomm
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DDR - Physical Design Engineer (Sr. Lead/Staff/Sr Staff)

DDR - Physical Design Engineer (Sr. Lead/Staff/Sr Staff)

Qualcomm

6 - 8 years

16 - 20 Lacs

Bengaluru

Posted:1 month ago| Platform:

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Skills Required

sta timing analysis signal integrity perl tcl technical writing python physical design cts primetime hardware engineering lvs rtl floorplan staffing physical verification floor planning awk drc timing closure pnr gds scripting languages

Work Mode

Work from Office

Job Type

Full Time

Job Description

Job Area: Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.This requirement is for DDR PD team for Bangalore. Number of openings:

Sr. Lead (6 to 8 years) 2

Staff (8 to 10 years) 1

Sr Staff (10 to 12 years) 1

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling

Hands-on experience with STA tools - Prime-time, Tempus

Have experience in driving timing convergence at Chip-level and Hard-Macro level

In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,

Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)

Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.

Proficient is scripting languages – TCL, Perl, Awk

Basic knowledge of device phy

STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs Qualcomm Hexagon DSP IP's .

Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.

Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.

Evaluate multiple timing methodologies/tools on different designs and technology nodes.

Work on automation scripts within STA/PD tools for methodology development.

Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment

Experience in design automation using TCL/Perl/Python.

Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus

Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo.

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DDR - Physical Design Engineer (Sr. Lead/Staff/Sr Staff)