DDR - Physical Design Engineer (Sr. Lead/Staff/Sr Staff)

General Summary: Qualcomm is a global leader driving next-generation innovations in technology, pushing boundaries to enable smarter, connected experiences. As a Qualcomm Hardware Engineer in the DDR Physical Design (PD) team, you will be involved in planning, designing, optimizing, verifying, and testing advanced electronic systems including circuits, mechanical, Digital/Analog/RF/optical systems, test systems, FPGA, and DSP systems. You will collaborate closely with cross-functional teams to meet stringent performance and timing requirements for cutting-edge products. Positions & Experience Levels: Senior Lead: 6 to 8 years of experience (2 openings) Staff Engineer: 8 to 10 years of experience (1 opening) Senior Staff Engineer: 10 to 12 years of experience (1 opening) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field + 6+ years experience OR Master's degree + 5+ years experience OR PhD + 4+ years experience in Hardware Engineering or related field Key Technical Skills & Responsibilities: Static Timing Analysis (STA): Strong fundamentals in STA timing analysis, including AOCV/POCV concepts, CTS, timing constraints, latch transparency, 0-cycle and multi-cycle path handling Hands-on experience with STA tools like PrimeTime and Tempus Driving timing convergence at both Chip-level and Hard-Macro level STA setup, convergence, review, and sign-off for multi-mode, multi-voltage domain designs (including Qualcomm Hexagon DSP IPs) Signal Integrity and Parasitics: Deep understanding of cross-talk noise, signal integrity, layout parasitic extraction, and feed-through handling ASIC Back-end Design: Knowledge of back-end flows and tools such as ICC2, Innovus Experience with circuit simulations using Hspice, FineSim, and Monte Carlo methods Correlation between silicon and spice simulation models Scripting and Automation: Proficient in scripting languages: TCL, Perl, Awk Experience with automation scripting for STA and physical design tools Familiarity with design automation flows from RTL to GDS (using tools like ICC, Innovus, PrimeTime, Tempus) Process Technology: Basic device physical knowledge Familiarity with process technology enablement and related simulations Soft Skills: Strong technical writing and communication skills Willingness to work collaboratively in a cross-functional and global environment