426 Compiler Jobs - Page 2

We are looking for an accomplished Engineering Manager to lead the PTX Compiler Team. Join the PTX Compiler team and help drive PTX language design and PTX compiler evolution. PTX enables all GPU Computing applications including Generative AI, ML/DL, HPC. PTX provides a stable programming model and portable instruction set Architecture (ISA) for NVIDIA GPUs and used by all Compute programming languages compiled to NVIDIA GPUs. PTX is also used as a compiler target by various non-NVIDIA compilers. You will lead a team that develops PTX ISA for new GPUs. Work with NVIDIA GPU Architecture and CUDA Programming model teams to build abstractions to expose new GPU features in portable and performant ways in PTX ISA. You will be contributing towards evolving programming model for Generative AI and DL applications on GPUs. You will be solving challenging problems working alongside some of the top minds in GPU computing and systems software. See your leadership efforts in action as HPC and DL developers use PTX to program new GPUs. What You Will Be Doing You will provide administrative and technical direction to a team of 3-6 system software development engineers, including planning, scheduling and execution of projects and activities. Provide stewardship for PTX ISA and PTX Compiler infrastructure for Generative AI and DL. Coordinate cross functional development with rest of the compiler stack. Working with customers/partners to gather feedback and drive innovative ideas and features to incorporate into the product. Drive schedule execution and quality, software engineering practices. Recommend changes to policies and establish procedures that affect immediate organization. Communicate with senior management for team vision and development progress. Groom future engineering leaders and mentor junior engineers. What We Need To See BS or MS degree in Computer Science, Computer Engineering , or related fields with a minimum of 10 overall years of experience with 3 years as manager in the area of low level system SW development related to compiler, linkers, loaders, binary tools. Superb analytical and C/C++ programming skills Experience in any one area of compiler development including feature support, code generation and compiler infrastructure Excellent and strong interactive, verbal and written communications skills. Understanding of Assembly Language / Processor ISA (GPU ISA not mandatory but a plus) Good track record of developing, driving and delivering software products. Ways To Stand Out From The Crowd Experience in Programming Languages design and drafting programming language standards. Knowledge of GPU development and compute APIs such as CUDA, and OpenCL. Development experience in LLVM IR, MLIR JR2000826

Company Size Startup / Small Enterprise Experience Required 3 - 7 years Working Days 5 days/week Office Location Remote Working Role & Responsibilities You will be working with the Rust compiler and will be responsible for compiling to alternate targets such as WebAssembly You will be exposed with TDD for unit testing individual functions and integration testing for testing publicly exposed APIs Working with a Git style workflow where every commit deploys to a stagingenvironment and merged pull requests deploy to production Setting up CI/CD pipelines for testing and deployment (canary, staging) using Github actionsaccording to project needs Developing software in Rust Maintaining and improving existing rust codebases. Ideal Candidate Excited about working with Rust 4 -7 years of experience in shipping production applications B.Tech in Computer Science Engineering from Tier 1 Colleges only Entrepreneurial mindset with strong decision-making skills Ability to move quickly without breaking things too much (we are dreamers) Ability to work under immense pressure which is balanced by a sense of responsibility and ownership Skills: tdd,webassembly,git,rust,github actions,github,ci,decision-making,enterprise,ci/cd,cd

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Our power efficient GPU solution is fundamental to enable new exciting markets like VR, IoT, AI, drone, autonomous driving etc. GPU compiler is a key component of graphics solution. We are looking for talented, self-motivated engineers to create world class GPU compiler products to enable high performance graphics and compute with low power consumption. The engineers will actively work with compiler developers on testing/verification for various graphics languages and development targets, as well as develop high quality automation tools. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Required Good hands-on experience of test methodology and test processes, including requirements collection and test plan development, testing automation and verification techniques. Strong understanding of Software Releases, Integration, and configuration management process/tools (Git, Make, CMake, MSBuild, JIRA, Perforce, etc.) Familiar with product software development/integration and release process/strategy Plan and execute product software integration/testing and build/release Good knowledge in programming using any scripting languages [Python/Perl] Good knowledge in Tools/Automation development – C/C++, Python/Django, Database Good communication at multiple levels and across multiple disciplines. Ability to work on Windows, Linux, and Android environments Self-motivated, adaptable, and independent, capable of working with limited supervision, pro-actively reporting on status and tasks. 2 to 10 years of hands-on experience in the above areas. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

About Us Yral is a decentralized social media platform (like TikTok) with integrated Prediction Markets, built on Internet Computer Protocol. The platform provides monetization avenues for 4.65 Billion social media lurkers (passive users) by enabling them to speculate on the short-video content created by other users on the platform. The vision is to create a user-driven and governed social media ecosystem with the users in the center. Not only would the users be given the majority share of the wealth that is being generated in the ecosystem, but the users will also have complete control over the various aspects of the platform such as governance, content moderation, development, and management, making the ecosystem more equitable and user-centric. We, at Yral, are looking for an experienced Rust developer to help us build an internet scale backend. About the Role We're building our backend on the Internet Computer which promises web scale serverless backends hosted on trustless decentralized infrastructure. Our ideal candidate is: Excited about working with Rust 4 -7 years of experience in shipping production applications BTech in Computer Science Engineering from Tier 1 Colleges desirable Understand the finer details of working with the Rust compiler and compiling to alternate targets such as WebAssembly Experienced with TDD for unit testing individual functions and integration testing for testing publicly exposed APIs Comfortable working with a Git-style workflow where every commit deploys to a staging environment and merged pull requests deploy to production Able to set CI/CD pipelines for testing and deployment (canary, staging) using GitHub actions according to project needs Entrepreneurial mindset with strong decision-making skills Ability to move quickly without breaking things too much (we are dreamers) Ability to work under immense pressure which is balanced by a sense of responsibility and ownership Visit us at Website: yral.com Twitter : https://x.com/Yral_app Linkedin: https://www.linkedin.com/company/yral-app/ Instagram: https://www.instagram.com/yral_app/ Instagram India: https://www.instagram.com/yralindia/ Telegram: https://t.me/HotOrNot_app Telegram Updates Channel: https://t.me/YRAL_app Discord: https://discord.com/invite/GZ9QemnZuj Please share your resumes or queries at nitya@gobazzinga.io

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 8 - 15 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid #DVT

Job Title: RTL Design Engineer Experience: 3–5 Years Company: eInfochips (An Arrow Electronics Company) Location: Ahmedabad/ Noida Job Type: Full-Time Job Description: eInfochips is looking for talented RTL Design Engineers with 3–5 years of experience in digital design. You will be working on IP and SoC-level RTL development for leading semiconductor clients across domains like Automotive, Consumer, Industrial, and AI. Key Responsibilities: RTL design using Verilog/SystemVerilog for IP and SoC subsystems Perform synthesis, linting, CDC/RDC analysis Interface with verification, physical design, and architecture teams Support SoC integration and debug Ensure design quality and timing closure Required Skills: 2+ years of hands-on RTL design experience Strong in digital design concepts (FSMs, pipelining, FIFOs) Proficient with tools like Synopsys Design Compiler, SpyGlass, VCS Experience with standard protocols (AXI, AHB, APB) Basic scripting skills (TCL, Perl, Python) How to Apply: 📩 Send your resume to: Nshalini.singh@einfochips.com

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Developing best-in-class architecture for Analog Mixed Signal IPs and high-speed parallel PHY interface solutions for next generation NAND flash memory controllers in advanced CMOS technology nodes. Interact with cross-functional teams to define requirements/specs, conceive the optimal solution by evaluating architectures, drive implementation, closely work with layout designers in guiding and reviewing the layouts, ensure timely and high-quality deliverables, extend SOC integration support and review and provide support for post-silicon activities from IP characterization to yield improvement and RMA. Provide good technical leadership in problem solving, planning and mentoring junior and senior engineers. Propose innovative design solutions and design methodologies. Fostering innovation culture and developing efficient processes by adopting state-of-the-art technologies. Qualifications Must have Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Working experience (20+ years) in IO including 5+ years as a project leader Should have architected and lead high speed interface design solutions from specification through Silicon debug and characterization Should have hands-on experience in TX and RX design architectures for high speed applications such as DDR4/DDR5/LPDDR4/LPDDR5 along with timing budget analysis. Should be experienced in high speed design architectures such as SERDES, Equalization schemes Should have hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant and Fail-safe IOs, Crystal oscillator etc. Should have extensive experience in ESD circuits design, Associated ESD guidelines and recommendations in different process nodes, IO and SOC level ESD review and signoff Experience in full custom high speed data path design such as DDR PHY will be of advantage. Conversant with tools such as Cadence Virtuoso/Synopsys custom compiler/Hspice/Spectre/Finesim including statistical simulation methodologies Experience in Mixed-mode simulation and analog/digital co-simulation will be of added advantage. Experience in creating EDA model such as Verilog model, Liberty etc will be of added advantage. Should have deep understanding and working knowledge of CMOS process including FINFET technologies such as 16nm/7nm/5nm and the associated DFM issues. Very analytical in nature and able to work in a multi-disciplinary environment Creative, out-of-the-box thinker with a high level of personal involvement Strong theoretical background with a pragmatic approach. Good verbal and written communication skills and experience working with different geographies. Good mentoring, documentation and presentation skills Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world We are currently in need of a highly skilled and motivated DevOps Engineer to join our Compiler Team at NVIDIA. This position provides a unique chance to work alongside a world-class engineering team passionate about building the next generation of compiler technologies. We enhance, maintain the build infrastructure and deliver new libraries, executables etc. for new compiler features to better realize the potential of NVIDIA GPUs for a growing range of computational workloads, ranging from deep learning, scientific computation, and self-driving cars to graphics workloads for AAA game titles on gaming platforms. Our compiler organization makes its mark on every GPU NVIDIA produces . What You'll Be Doing Develop and maintain robust CI/CD pipelines to ensure flawless integration and delivery of software. Collaborate with multi-functional teams to improve the efficiency and reliability of build systems. Monitor and optimize system and build performance, ensuring flawless operation Implement and manage containerization and orchestration tools like Docker and Kubernetes to streamline development workflows. Diagnose and resolve complex issues, ensuring the stability and performance of our environments. What We Need To See Bachelor's degree in Computer Science, Engineering, or a related field, or equivalent experience. 3+ years' work experience in software development or DevOps roles. Proven experience with GNU Make, CMake, Bazel, or similar build tools. Proficiency in Docker, Jenkins (Groovy), GitLab CI/CD, Artifactory, Ansible, and Kubernetes. Strong understanding of version control systems, including Perforce and Git. Expertise in scripting languages such as Python or Bash. Outstanding problem-solving skills and the ability to determine root causes and implement effective solutions. Strong communication skills and a collaborative team spirit. Prior experience of LLVM build would be advantage. Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/ NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. JR1999332

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world We are currently in need of a highly skilled and motivated DevOps Engineer to join our Compiler Team at NVIDIA. This position provides a unique chance to work alongside a world-class engineering team passionate about building the next generation of compiler technologies. We enhance, maintain the build infrastructure and deliver new libraries, executables etc. for new compiler features to better realize the potential of NVIDIA GPUs for a growing range of computational workloads, ranging from deep learning, scientific computation, and self-driving cars to graphics workloads for AAA game titles on gaming platforms. Our compiler organization makes its mark on every GPU NVIDIA produces . What You'll Be Doing Develop and maintain robust CI/CD pipelines to ensure flawless integration and delivery of software. Collaborate with multi-functional teams to improve the efficiency and reliability of build systems. Monitor and optimize system and build performance, ensuring flawless operation Implement and manage containerization and orchestration tools like Docker and Kubernetes to streamline development workflows. Diagnose and resolve complex issues, ensuring the stability and performance of our environments. What We Need To See Bachelor's degree in Computer Science, Engineering, or a related field, or equivalent experience. 3+ years' work experience in software development or DevOps roles. Proven experience with GNU Make, CMake, Bazel, or similar build tools. Proficiency in Docker, Jenkins (Groovy), GitLab CI/CD, Artifactory, Ansible, and Kubernetes. Strong understanding of version control systems, including Perforce and Git. Expertise in scripting languages such as Python or Bash. Outstanding problem-solving skills and the ability to determine root causes and implement effective solutions. Strong communication skills and a collaborative team spirit. Prior experience of LLVM build would be advantage. Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/ NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. JR1999332

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 8 - 15 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #DVT

At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Location: Bangalore/Kolkata Experience: 3+ years Opportunity Snapshot: We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills. You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems. You will have a significant opportunity to interact with system design teams across geographies. Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture. Thus, you set your own limits for learning, achievements and rewards. Responsibilities: Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes Required Skills: 3+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required About Juniper Networks Juniper Networks challenges the inherent complexity that comes with networking and security in the multicloud era. We do this with products, solutions and services that transform the way people connect, work and live. We simplify the process of transitioning to a secure and automated multicloud environment to enable secure, AI-driven networks that connect the world. Additional information can be found at Juniper Networks (www.juniper.net) or connect with Juniper on Twitter, LinkedIn and Facebook. WHERE WILL YOU DO YOUR BEST WORK? Wherever you are in the world, whether it's downtown Sunnyvale or London, Westford or Bengaluru, Juniper is a place that was founded on disruptive thinking - where colleague innovation is not only valued, but expected. We believe that the great task of delivering a new network for the next decade is delivered through the creativity and commitment of our people. The Juniper Way is the commitment to all our colleagues that the culture and company inspire their best work-their life's work. At Juniper we believe this is more than a job - it's an opportunity to help change the world. At Juniper Networks, we are committed to elevating talent by creating a trust-based environment where we can all thrive together. If you think you have what it takes, but do not necessarily check every single box, please consider applying. We’d love to speak with you. Additional Information for United States jobs: ELIGIBILITY TO WORK AND E-VERIFY In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire. Juniper Networks participates in the E-Verify program. E-Verify is an Internet-based system operated by the Department of Homeland Security (DHS) in partnership with the Social Security Administration (SSA) that allows participating employers to electronically verify the employment eligibility of new hires and the validity of their Social Security Numbers. Information for applicants about E-Verify / E-Verify Información en español: This Company Participates in E-Verify / Este Empleador Participa en E-Verify Immigrant and Employee Rights Section (IER) - The Right to Work / El Derecho a Trabajar E-Verify® is a registered trademark of the U.S. Department of Homeland Security. Juniper is an Equal Opportunity workplace. We do not discriminate in employment decisions on the basis of race, color, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic. All employment decisions are made on the basis of individual qualifications, merit, and business need.

📢 Hiring: Assistant Professor – Computer Science & Engineering (CSE) We are inviting applications for the position of Assistant Professor in the Department of Computer Science & Engineering. 🧠 We are particularly looking for passionate educators in the following subject areas: Theory of Computation Compiler Design Discrete Structure Advanced Data Structures & Algorithms 🎓 Eligibility: A strong academic background in CSE or related disciplines. GATE qualification will be preferred. 📍 If you're driven by academic excellence and a passion for shaping the next generation of engineers, we would love to hear from you! Please feel free to like, share, or tag someone who might be a great fit.

About The Role Uber's data infrastructure is composed of a wide variety of compute engines, scheduling/execution solutions, and storage solutions. Compute engines such as Apache Spark™, Presto®, Apache Hive™, Neutrino, Apache Flink®, etc., allow Uber to run petabyte-scale operations on a daily basis. Further, scheduling and execution engines such as Piper (Uber's fork of Apache Airflow™), Query Builder (user platform for executing compute SQLs), Query Runner (proxy layer for execution of workloads), and exist to allow scheduling and execution of compute workloads. Finally, a significant portion of storage is supported by HDFS, Google Cloud Storage (GCS),Apache Pinot™, ElasticSearch®, etc. Each engine supports thousands of executions, which are owned by multiple owners and sub-teams. With such a complex and diverse big data landscape operating at petabyte-scale and around a million applications/queries running each day, it's imperative to provide the stakeholders a holistic view of the right performance and resource consumption insights. DataCentral, is a comprehensive platform that provides users with essential insights into big data applications and queries. It empowers data platform users by offering detailed information on workflows and apps, improving productivity by reducing debugging time and improving the cost efficiency by providing detailed resource efficiency insights As an engineer in the Data Central Team, you will be solving some of the most complex problems in Observability and efficiency of Distributed Data Systems at Uber scale. What You'll Do Work with Uber data science and engineering teams to improve Observability of Batch Data use-cases at Uber. Leverage knowledge of spark internals to dramatically help improve customer's Spark job performance. Design and implement AI based solutions to improve the application debuggability. Design and implement algorithms to optimize Resource consumption without impacting reliability Design and develop prediction and forecasting models to proactively predict system degradations and failures Work with multiple partner teams within and Uber and build cross-functional solutions in a collaborative work environment. Work with the community to upstream Uber's contributions to open source and also keep our internal fork up to date What You'll Need Bachelor's degree in Computer Science or related field. 5+ years of experience building large scale distributed software systems. Solid understanding of Java for backend / systems software development. MS / PhD in Computer Science or related field. Experience managing production systems with a strong availability SLA. Experience working with Apache Spark or similar analytics technologies. Experience working with large scale distributed systems, HDFS / Yarn. Experience working with SQL Compiler, SQL Plan / Runtime Optimization. Experience working with Kubernetes

About Company Gevme is a Singapore based fast growing leading virtual & hybrid event and engagement platform for building unique experiences. It is used by event professionals worldwide to build, operate and monetise virtual events for some of the biggest brands. The flexibility of the platform provides them with limitless possibilities to turn any virtual event idea into reality. We have already powered hundreds of thousands of events around the world for clients like Facebook, Netflix, Starbucks, Forbes, MasterCard, Singapore Government. We are a product company with a strong engineering and family culture; we are always looking for new ways to enhance the event experience and empower efficient event management. We’re on a mission to groom the next generation of event technology thought leaders as we grow. Join us if you want to become part of a vibrant and fast moving product company that's on a mission to connect people around the world through events. Location: Remote/Work from Home Responsibilities Design, develop, and maintain both front-end and back-end components of web applications using the MERN stack. Build robust and secure RESTful APIs using Express.js and Node.js to serve data to the front-end. Design and manage MongoDB databases, ensuring data integrity and performance. Create responsive and user-friendly web interfaces using React. Write unit and integration tests to ensure code quality and functionality. Collaborate with designers, product managers, and other engineers throughout the development lifecycle. Troubleshoot and debug issues in both front-end and back-end code. Optimize application performance for speed and scalability. Stay up-to-date with the latest technologies and trends in web development. Qualifications Computer Science Graduate. Minimum of 2 years of proven experience on the implementation of large-scale web applications. Strong proficiency in JavaScript and TypeScript. Extensive experience with the MERN stack (MongoDB, Express.js, React, Node.js). Solid understanding of front-end development principles and best practices. Experience with front-end tooling like Vite.js. Experience with Next.js for building performant React applications. Proficiency in building RESTful APIs. Experience with Git for version control. Familiarity with testing frameworks like Jest or Mocha. Excellent problem-solving skills and ability to adapt to a fast-paced environment. Strong communication and collaboration skills. Bonus Points (Optional) Experience with Fastify for building high-performance Node.js applications. Familiarity with NestJS for building scalable server-side applications. Experience with Electron.js for developing cross-platform desktop applications. Experience with compiler tools like Webpack or SWC. Skills:- MongoDB, NodeJS (Node.js), React.js, Express, MERN Stack, Javascript, RESTful APIs, TypeScript and Vite.js

Syniverse is the world’s most connected company. Whether we’re developing the technology that enables intelligent cars to safely react to traffic changes or freeing travelers to explore by keeping their devices online wherever they go, we believe in leading the world forward. Which is why we work with some of the world’s most recognized brands. Eight of the top 10 banks. Four of the top 5 global technology companies. Over 900 communications providers. And how we’re able to provide our incredible talent with an innovative culture and great benefits. Who We're Looking For A Sr Software Development Engineer has the responsibilities to develop new applications and perform lifecycle support for existing applications. The engineer must possess in depth knowledge of a sub system within the environment and the tools that support company’s products. The engineer must also attend and contribute in internal team meetings. In addition, the engineer must be completely accountable for all assigned tasks. Finally, the engineer is required to adhere to all of company’s software development procedures and processes while fulfilling the leadership role. Some of What You'll Do Scope of the Role: Direct Reports: This is an individual contributor role with no direct reports Key Responsibilities Development of software modules conforming to the functional/ performance/ user experience requirements Development and automation and execution of Unit and Functional Tests to demonstrate the conformance of software with the functional/ performance/ user experience requirements Modify existing software to correct errors, to adapt it to new hardware, or to upgrade interfaces and improve performance. Create high-level or detailed design documents from requirements utilizing Object-Oriented or Structured Methods that contain such items as use cases, flow diagrams, structure definitions and architecture diagrams. Modify existing software to correct errors, to adapt it to new hardware, or to upgrade interfaces and improve performance Ensure software security by developing programs to actively monitor the sharing of private information Integration testing across interfacing functional groups that may be involved, such as Crossroads, billing and reporting. On-boarding new customers by verifying network connections to a customers’ network, assisting in troubleshooting connections problems, and configuring the production system with customer-specific application parameters. Analyzing causes for outages by reviewing logs, viewing queues, monitoring message links. Review design documents, code and test results to insure accuracy and completeness and adherence to the requirements. Document thorough release notes detailing the implementation process according to company procedures. Present the implementation plan in formal release planning walk-thrus. Assist operations with the actual implementation of an application. Perform post-implementation monitoring and testing to insure the release is functioning as expected. Work with Product Support to research customer reported problems. Analyze application logs, network traces and program traces to determine the root cause of reported problems. Using company’s test environment and emulation tools, duplicate problematic scenarios reported by the customer. Experience, Education, and Certifications: (What are the minimum years of experience, education, or certifications needed) Bachelor of Engineering/ Bachelor of Technology (B.E/ B.Tech) and/or postgraduate of computer science (M.Sc./MCA) with basic knowledge in JAVA, Unix, Shell Scripting, RDBMS concepts, PL/SQL 5+ years of working technical experience in coding, testing, supporting, troubleshooting, designing, building, installing, configuring, and supporting Unix servers and storage servers and management software Working experience in : Development environment – OS, editor, utilities, database. Compiler, Debugger. Java, C, C++ Languages. Production runtime environment. Object-Oriented and Structured development methodologies. RDBMS, SQL. ISPF, JCL/PROC. COBOL, REXX, Easytrieve, Clist. VSAM, DB2. File-Aid, Expeditor, ESP. Additional Requirements: Ownership/Accountability for tasks/projects. Work well within a team environment. Excellent oral and written communication skills. Independent work habits. Proven ability to deliver quality software on time. Act with a sense of urgency. Positive attitude - optimism. Maintain composure in a stressful environment. Strong analytical, business logic and problem resolution skills. Strong control and follow-up skills. Solid decision making skills. Project Management knowledge. Why You Should Join Us Join us as we write a new chapter, guided by world-class leadership. Come be a part of an exciting and growing organization where we offer a competitive total compensation, flexible/remote work and with a leadership team committed to fostering an inclusive, collaborative, and transparent organizational culture. At Syniverse connectedness is at the core of our business. We believe diversity, equity, and inclusion among our employees is crucial to our success as a global company as we seek to recruit, develop, and retain the most talented people who want to help us connect the world. Know someone at Syniverse? Be sure to have them submit you as a referral prior to applying for this position.

Location: Hybrid Job Type: Full-Time Posted Date: 6/30/2025 About The Role Job Overview: We are seeking a Senior Physical Design Engineer with strong expertise in Netlist-to-GDSII implementation and experience working on advanced submicron technology nodes. The role demands in-depth knowledge of industry-standard EDA tools and a solid grasp of timing closure and physical verification processes. Key Responsibilities:  Drive full Netlist-to-GDSII flow: floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.  Perform Static Timing Analysis (STA) and ensure timing closure across all design corners.  Execute power integrity and physical verification checks (LVS, DRC).  Collaborate closely with cross-functional teams (RTL, STA, packaging, and DFT).  Handle complex designs on 28nm and below technology nodes. Must-Have Skills  Strong hands-on experience with: o Synopsys/Cadence tools: Innovus, ICC2, Primetime, PT-PX, Calibre o Physical Design Methodologies: Floorplanning, Placement, CTS, Routing, STA  Proficiency in: o Timing constraints and closure o Tcl/Tk/Perl scripting o Submicron nodes (28nm and below) Good to Have  Familiarity with Fusion Compiler  Broader understanding of signal and power integrity  Experience in workflow automation and tool scripting If you are interested in this role, please mail your resume to hemanth@neualto.com or spoorthy@neualto.com.

*Candidates from Pan India can apply *Positions in International Languages *Able to speak well & understand Nepali along with Excellent english speaking is must *Outstanding verbal & listening skills *Salary upto 45k CTC Barkha @ 8851644223 Required Candidate profile *Any dropout/12th pass/UG and Graduate (Fresher & experienced)can apply *5days working *Permanent work from home *Telephonic Interview *Open to work-rotational shifts * Pan India * 2week offs Perks and benefits Permanent work from home (+ Incentives)

GL Bajaj (Institute of Technology & Mgmt.) – A Glimpse! Passionate education provider in multi disciplines at undergraduate and postgraduate level (B.Tech, MBA, MCA) Vibrant Learning Ecosystem on the campus, has inspired and brilliant students. GL Bajaj Group was incepted in year 1997 , carrying a winning legacy of 12 institutions running diverse higher education programs. GL Bajaj Group, has +14,000 students, +800 faculty members , 12 institutions, and 6 campuses with +300 acres of land. NAAC A+ accredited, 4 stars from Ministry of Education, NIRF rank holder, Research & Incubation centre, Entrepreneurship development and top quality placement for students Vision to give globally competent & socially sensitive professionals to the society. Highly inquisitive students who take risks, experiment, and put novel ideas into action. Sharpens the Technical as well as Life Skills of students – Developing young leaders. Have world class collaborative LEARNING infrastructure for teaching & learning practices. Hiring Distinguished faculty members from the Institutes of repute . We nurture versatile INTRAPRENEURs . Our core belief is in nurturing Diverse, inclusive, equity knowledge gems Hi – Tech Campus has a beautiful , serene environment & students enjoy learning. Believes in relentless change and desire to improve . We are looking for passionate researchers/out of box thinkers/academicians who have a go-getter attitude, have fire to innovate , works with technology driven progressive mindset and execute the concept of sustainability in each task ( paperless ) in learning process delivery. We are offering to the right candidate an excellent compensation package along with the tools and the environment to foster intellect and new ideas. If you want to CONTRIBUTE meaningful to the society at large, join us & Find your SPARK! ABOUT JOB Designation: Assistant Professor Job Purpose & Role: To teach, research and serve the Institution for academic, institutional & student’s growth & development. WORK Responsibilities: 1 LEARNING & TEACHING To develop and teach undergraduate and graduate courses in CORE Computer Science & Allied courses. Command on Subjects like: Programming Fundamentals via language C/C++, JAVA, Python Data Structures & Algorithms Operating Systems Computer Architecture & Organisation Object Oriented Programming (OOP) Software Engineering Design & Analysis of Algorithms Computer Networks, Compiler Designs, DevOps Artificial Intelligence, Machine Learning Deep Learning, Natural Language Processing, Computer Vision, or related areas. etc. Proven experience of teaching new age subjects like Cybersecurity, Big Data Analytics, IoT, Cloud Computing, Blockchain Technology, AVR (Augmented & Virtual Reality) with a commitment to innovative pedagogical approaches. Have an ability to stay abreast on the latest emerging trends and technologies in AI/AIML/DS such as reinforcement learning, generative models, or ethical AI. To stay abreast of developments in the field of AI through continuous learning, attending conferences, and networking with peers. Proven e xperience with software development and programming languages commonly used in AI research, such as Python, TensorFlow, PyTorch, or similar tools. To make best use of technology in teaching learning methodology. Proven experience of excellent delivery of the subject for the students by active or activity based learning, real-life problem solving approaches in content delivery and achieve the best results /awards/positions in the university. To fulfill responsibility concerning students in respect of instruction, progress, and examination. To prepare / maintain lesson plans, lecture notes, model question papers, attendance register, manual etc. To ensure discipline and welfare of the students . To meaningfully engage students in class, seminars, workshops, conferences , events, applied subject knowledge projects. To ensure Quality (NBA, ISO, NAAC, NIRF) and innovative education to students by continuous monitoring of subject, books, and journals, teaching aids, Laboratory facilities and ensure understanding of education regulatory bodies like UGC / AICTE 2 RESEARCH To conduct cutting-edge research in AI, Data Science, AIML, Core CSE , publish findings in reputable journals and conferences, and pursue external funding to support research activities. To supervise and mentor graduate students, providing guidance and support in their research endeavours To collaborate with industry partners to apply AI/AIML techniques to real-world problems and foster technology transfer. To have an ability to secure external research funding and lead research projects independently or collaboratively. Proven experience in working with interdisciplinary research teams or collaborating across departments. To facilitate in connecting industry with academia for providing hands on experience leading to skill development of students. To do quality research, have good academic record and books/research paper publications/IPR/patents record. To continue to develop one’s position as a leading researcher, including publication, external funding and the pursuit of other relevant indicators of standing in the field. 3 GL Bajaj’s Citizenship and Ownership of Responsibilities To participate in continuing professional development e.g. through seminars or conferences and by engaging in training programmes run by the Institution which are consistent with the needs and aspirations of the academics. To support, mentor and facilitate seminars, trainingactivities, cross-departmental activities and events and Ceremonies etc. To demonstrate the GL Bajaj’s values throughown actions and behaviour . To undertake such other duties as may be reasonably requested and that are commensurate with the nature and grade of the post. To engage in continuous personal and professional development in line with the demands of the role, including undertaking relevant training and development activities to develop themselves and support the development of others. To ensure and promote the personal health,safety and wellbeing of staff and students. To carry out duties in a way which promotes fairnessin all matters , and which engenders trust. APTITUDE & SKILLS 1 Functional Skills Passionate Academician/Researcher Competency of Nurturing Students Excellent interpersonal & content delivery skills. Ability to engage students constructively. Academic domain knowledge – National (UGC/NBA/NAAC/NIRF/AICTE etc.)/International Highly developedcommunication and presentation skills to present research findings at national and international conferences Ability to harness IT as a research and teaching tool A willingness to undertake further training as appropriate and to adoptnew procedures as and when required 2 Attributes Dynamic, energetic, team player, thrives among strong colleagues. Ability to work in fast paced evolving environment . Be willing and able to exercise judgment and take risks. Accept criticism and constructive feedback , while being extremely adaptable and flexible. Reflection of an impeccable persona in walk-talk while dealing with academia High emotional intelligence Qualification & Years of Experience as per AICTE/UGC norms: B.Tech & M.Tech – IT/CSE from Top tier Institutes & reputed universities like IITs, NITs, IIITs, IISc. Etc. and throughout first class 0-4 years of experience in teaching/ research PhD or PhD (Pursuing) candidates from Top Institutes will be preferred Industry Experience is desirable. Salary as per current norms Location: Greater Noida, Delhi/NCR Apply for the position by sending your CV on careers@glbitm.ac.in You may visit our website’s career page at www.glbitm.org

Company Description Spandsons Horizon Engineering revolutionises the AEC industry by integrating sustainability, Design & Build of Infrastructures, Structural Engineering, AI, IoT, and innovative technologies into project management, Virtual Design Construction, and training programs. We are at the forefront of blending advanced technological solutions with environmental consciousness to drive progress and innovation. Our mission is to deliver cutting-edge engineering solutions while fostering a culture of continuous learning and development. Role Description This is a contract role for a VLSI Mentor / Guest Faculty specialising in Advanced Digital Systems & Low Power Design. This is an on-site role located in Salem. You will be instrumental in guiding 5th, 6th, and 7th-semester B.E./B.Tech students in advanced VLSI concepts and practical applications. This role offers a unique opportunity to directly impact the academic and career growth of 60 aspiring engineers. Key Responsibilities: Deliver engaging and in-depth sessions on: Advanced Digital System Design with Verilog HDL: Covering topics from Verilog HDL basics, combinational and sequential circuits, FSM design, to simulation and testing. Low Power VLSI Design: Including the need for low power design, power estimation and optimisation, dynamic power reduction techniques, clock/power gating, and leakage reduction techniques. Potentially other VLSI domains such as Digital Design Verification with SystemVerilog & UVM, Introduction to FPGA-Based Digital System Design, ASIC Design and Verification, and Introduction to RISC-V Architecture and FPGA Design, based on program needs. Provide hands-on guidance for lab assignments and projects, utilising tools like Xilinx Vivado, EDA Playground, ModelSim/Vivado, LTspice, Synopsys Design Compiler, ICC2, PrimeTime, VCS, Verdi, and FPGA boards. Facilitate interactive learning and encourage problem-solving among students. Ensure alignment of content with the recommended semester curriculum and prerequisites. Qualifications: Minimum of 4-5 years of verifiable industry experience in VLSI design, with strong expertise in Advanced Digital System Design and Low Power VLSI Design. Proficiency in relevant EDA tools and hardware platforms as listed above. Excellent communication and presentation skills. A passion for teaching, mentoring, and contributing to student development. Program Details: Total Students: Approximately 60. Schedule: Thursdays & Fridays (12 hours per week). Program Start Date: July 24th & 25th. Duration: Program for Semesters 5, 6, and 7. Benefits: Accommodation and food will be provided by the institution. Opportunity to make a significant impact on the next generation of VLSI engineers. Collaborate with a forward-thinking academic institution.

Key Responsibilities: Drive block-level and/or full-chip physical design from RTL to GDSII. Floorplanning, placement, clock tree synthesis (CTS), and routing. Work on static timing analysis (STA) and timing closure. Run and debug physical verification (LVS/DRC/ERC) and power integrity checks (IR Drop/EM). Collaborate with RTL, DFT, synthesis, verification, and packaging teams. Ownership of PPA (Power, Performance, Area) targets and meeting timing goals. Participate in multiple tape-outs and manage block-level signoff closure. Automate and optimize flows using Tcl, Perl, Python, or shell scripting. Keep up-to-date with the latest EDA tools and technology trends. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field. 4–10 years of experience in physical design with successful tape-outs. Strong expertise in Synopsys/Cadence tools (ICC2, Fusion Compiler, Innovus, PrimeTime, etc.). Deep understanding of digital design concepts, timing, and power trade-offs. Hands-on experience in advanced technology nodes (16nm and below preferred). Experience with scripting languages (Tcl, Python, Perl, Shell). Familiarity with ECO flows, DFT insertion, and low-power design techniques (UPF/CPF). Knowledge of signal and power integrity issues (IR/EM) is a plus.

Logic Design Engineer II Bangalore, Karnataka, India Date posted Jul 21, 2025 Job number 1848527 Work site Up to 50% work from home Travel None Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for an SOC RTL to PD Engineer to join the team. Qualifications Required Qualifications: MS with 2+ years of experience or BS with 4+ years of experience. At least 3+ years of experience applying digital design principles in SOC and/or IP development. Strong Static Timing Analysis background; understanding timing signoff fundamentals. Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, and Innovus. Experience with timing constraints management and debug tools supporting constraints quality checks, constraints verification, constraints promotion & demotion. Through understanding in writing timing constraints, exceptions, clock constraints; good understanding in SDC commands and TCL constraints. Understanding in design closure challenges in power and clock domain crossings. Understanding reset and FIFO related design requirements. Preferred Qualifications Experience with FEV and industry standard tools such as Formality and/or Conformal Applied understanding of low power design principles. Highly Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Strong understanding in clock crossing techniques Strong understanding in IJPF (Low power intent). Ability to write scripts using Perl, TCI, Python etc. Familiarity with Industry standard interface protocols is a plus. Good verbal and written communication skills. Responsibilities Ensure high quality deliverables from RTL to Physical Design Learn custom synthesis flow and setup and an perform synthesis while ensuring high quality of results Create, analyze, and maintain timing constraints/SDCs Analyze and drive UPF solutions for low power checks Drive RTL to Synthesis FEV clean Collaborate with RTL and Physical Design team to address design feedback and drive quality Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER (AECG ASIC TFM Lead) THE ROLE: As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will work with design experts to come up with the best implementation methodologies/flows and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Define and drive key Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Excellent physical design and timing background. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Meta is hiring talented individuals to join our Infrastructure organization as ASIC Frontend Implementation Engineers (RDC/CDC). In this role, you will play a critical part in designing and developing efficient System on Chip (SoC) and IP for data center applications. As an ASIC Frontend Implementation Engineer, your primary focus will be on the front-end implementation process and static verification tools, transforming RTL designs into optimized netlists. You will utilize your expertise in RTL Lint, CDC analysis, timing constraints, and synthesis to ensure seamless integration of various components to build efficient System on Chip (SoC) and IP for data center applications.By joining our team, you'll have the opportunity to contribute to the development of cutting-edge technology that powers Meta's infrastructure. ASIC Engineer, Frontend Implementation RDC/CDC Responsibilities: Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power Developing Automation scripts and Methodology for all Front End (FE)-tools including (Lint, CDC, RDC,) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in static verification tools Experience with Lint, Clock Domain & Reset Domain crossing Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL Successful candidates must remain in role in the same team in India for a minimum period of 24 months before being eligible for transfer to another role, team or location Preferred Qualifications: Scripting and programming experience using Perl/Python, TCL, and Make Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Experience with SOC Design Integration and Front-End Implementation Experience with developing structural rule based checks for RTL & Netlist Experience with Netlist-CDC Analysis and improving MTBF Knowledge of Timing/physical libraries, SRAM Memories About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Schaeffler is a dynamic global technology company and its success has been a result of its entrepreneurial spirit and long history of private ownership. Does that sound interesting to you? As a partner to all of the major automobile manufacturers, as well as key players in the aerospace and industrial sectors, we offer you many development opportunities. General Information SW Developer designs, implements, develops source code and tests the SW units within a SW project. SW Developer integrates the SW Units / SW Components and ensures inter-operability between them. Your Key Responsibilities Detailed design, coding and unit testing of specific SW Components in accordance to the BU processes and conventions. Define the Requirements for the SW Function Design. Structure the SW Function Design. Design the SW Function Design in SDA. Code your Design Auto Code or in case there is a valid reason do it hand code. Perform development checks, reviews (e.g. design, code) & static code analysis. Perform SW units integration,Integrate the SW Code in corresponding repository under the valid integration rules and KPI’s. Perform SW Integration Test to verify SW architecture specification (acting as SW Integration Tester). Test – Verify your design before at Design level and after Integration (Integration level) by your own. Reuse and adaptation of existing SW Components or modules. Debug and root cause of reported issues of software module or component scope. Correction of anomalies as defined in the Problem Resolution process. Proactive communication of e.g. delays, possible risks, problems during development. Delivery of the committed work package results within the planned time, effort and quality. Get access rights to input work products, tools and infrastructure necessary to perform the assigned tasks, especially to the development/compiler toolchain, the CM/ChM System for this project inclusive access to related SW requirements, to the generic libraries or previous projects for re-use and also debugger, sample ECU or PCB with measuring equipment. Initiate / raise issues due to incorrect requirements, inconsistent architecture, erroneous or unreliable 3rd party software, etc. Initiate / raise issues on major insufficiencies within the development tool chain. Approving of SW Integration and SW Integration Test per SW Component. Your Qualifications Educational Qualification: Minimum B.E/B. Tech in Electronics & Communication Engineering or Master’s in Electronics Engineering will be an added advantage Experience: Minimum 4 years experience in Automotive software development Our Offering Great company culture and well-defined career path Opportunity to be a key part of a growing organization Close collaboration with customer and project-team As a global company with employees around the world, it is important to us that we treat each other with respect and value all ideas and perspectives. By appreciating our differences, we inspire creativity and drive innovation. In this way, we contribute to sustainable value creation for our stakeholders and society as a whole. Together, we advance how the world moves. Exciting assignments and outstanding development opportunities await you because we impact the future with innovation. We look forward to your application. www.schaeffler.com/careers Your Contact Vitesco Technologies India Pvt. Ltd. Hemanth Hurudi

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications: Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Scripting and programming experience using Perl/Python, TCL, and Make Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.