231 Compiler Jobs - Page 2

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Role Work on Logic & Physical aware Synthesis with Low Power, QoR optimization, STA and Netlist Signoff flows. Work on Logic equivalence check and low power check clean up. Work on constraints development by interacting with designers and help in porting constraints from block to top-level. Should be able to handle multiple projects by leading a team of 3 to 5 members and deliver. Should be able to lead implementation flow development effort independently by working closely with design team and EDA vendors. Should be able to drive new tool evaluation, methodology refinement for PPA optimization. Should be sincere, dedicated and willing to take up new challenges. Skill Set Proficiency in Python/Tcl. Familiar with Synthesis & STA tools (Fusion Compiler/Genus, Primetime/Tempus). Fair knowledge in LEC, LP signoff tools. Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3074218 Show more Show less

BENGALURU, KARNATAKA, INDIA FULL-TIME SOFTWARE ENGINEERING 3527 Waymo is an autonomous driving technology company with the mission to be the most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo One, a fully autonomous ride-hailing service, and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over one million rider-only trips, enabled by its experience autonomously driving tens of millions of miles on public roads and tens of billions in simulation across 13+ U.S. states. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate with many other teammates to ensure we design and improve hardware and software for maximum performance. We are a diverse team looking for curious and talented teammates to work on one of the world's highest performance automotive compute platforms. In this hybrid role, you will report to a Software Engineering Manager. You will: Maximize performance of our neural networks by enhancing and extending our production grade compiler Work with hardware architects and model developers to develop understanding of our unique neural network inference platform and neural networks Implement compiler support for novel features of our high-performance architecture You have: BS degree in Computer Science/Electrical Engineering or equivalent practical experience and 3+ years of industry experience OR MS degree in Computer Science/Electrical Engineering and 1+ years of industry experience OR PhD Degree in Computer Science/Electrical Engineering or equivalent years of experience 1+ years of industry and/or academic experience with compilers and parallel computing 1+ years of industry and/or academic experience working with ML inference or linear algebra computations C++ programming skills We prefer: Python programming experience Experience with compilers for neural networks Knowledge of computer architectures used for neural network inference, and neural network performance characteristics Knowledge of the principles behind popular machine learning and neural network algorithms and applications The expected base salary range for this full-time position is listed below. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. Salary Range ₹3,400,000—₹4,110,000 INR

BENGALURU, KARNATAKA, INDIA FULL-TIME SOFTWARE ENGINEERING 3528 Waymo is an autonomous driving technology company with the mission to be the most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo One, a fully autonomous ride-hailing service, and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over one million rider-only trips, enabled by its experience autonomously driving tens of millions of miles on public roads and tens of billions in simulation across 13+ U.S. states. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate with many other teammates to ensure the optimization of hardware and software for maximum performance. In this hybrid role, you will report to a Software Engineering Manager. You will: Analyze the performance characteristics of code generated by our production grade compiler, and design and implement optimizations to improve that performance Design and implement compiler support for novel features of our high-performance architecture Work with hardware architects to understand and influence the development of our unique neural network inference platform through hardware/software codesign Work with model developers to tune their neural networks for better inference efficiency and accuracy You have: BS degree in Computer Science/Electrical Engineering or equivalent experience and 5+ years of industry experience OR MS degree in Computer Science/Electrical Engineering and 3+ years of industry experience PhD degree in Computer Science/Electrical Engineering and 1+ years of industry experience 3+ years experience working on compilers for parallel architectures 1+ years experience working with ML inference or linear algebra computation C++ programming skills We prefer: Python programming experience Experience with compilers for neural networks Knowledge of computer architectures used for neural network inference, and neural network performance characteristics Knowledge of the principles behind popular machine learning and neural network algorithms and applications The expected base salary range for this full-time position is listed below. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. Salary Range ₹5,500,000—₹6,650,000 INR

We are looking for a Digital/Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! What You'll Be Doing Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies. Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes. Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows. Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks. Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies. Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts. Possess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions. Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability. Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives. Excel in resource management, representing the team in technical discussions with customers IP layout will comprise of significant digital components. Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts Follow company procedures and practices for IC layout activities. What We Need To See B.E/B Tech. / M Tech in Electronics or equivalent experience with 2+ years of proven experience in Memory layout in advanced CMOS process. Detailed knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance memories of various types. Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding) Experience with floor planning, block level routing and macro level assembly. Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status JR1997059 Show more Show less

We are looking for a Digital/Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! What You'll Be Doing Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies. Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes. Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows. Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks. Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies. Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts. Possess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions. Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability. Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives. Excel in resource management, representing the team in technical discussions with customers IP layout will comprise of significant digital components. Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts Follow company procedures and practices for IC layout activities. What We Need To See B.E/B Tech. / M Tech in Electronics or equivalent experience with 2+ years of proven experience in Memory layout in advanced CMOS process. Detailed knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance memories of various types. Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding) Experience with floor planning, block level routing and macro level assembly. Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. JR1997057 Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary: ) We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation. Qualifications BE/BTech/ME/MS/MTech in computer Science Job Responsibilities Hands on experience designing, developing, troubleshooting and debugging complex software Expertise in data structures, algorithms, operating systems, computer science concepts Expertise in compiler development, optimizations is highly desired Development experience using configuration management systems on large software Hands on experience with software quality hygiene tools for address, logic and static checkers Candidate should have strong experience in C/C++ and thorough knowledge of software development practices Strong debugging skills Team player with strong communication skills Knowledge of assembly language for x86, ARM is desired We’re doing work that matters. Help us solve what others can’t. Show more Show less

About Blaize Blaize provides a full-stack programmable processor architecture suite and low-code/no-code software platform that enables AI processing solutions for high-performance computing at the network’s edge and in the data center. Blaize solutions deliver real-time insights and decision-making capabilities at low power consumption, high efficiency, minimal size and low cost. Blaize has raised over $330 million from strategic investors such as DENSO, Mercedes-Benz AG, Magna, and Samsung and financial investors such as Franklin Templeton, Temasek, GGV, Bess Ventures, BurTech LP LLC, Rizvi Traverse, and Ava Investors. Headquartered in El Dorado Hills (Calif.), Blaize has more than 200 employees worldwide with teams in San Jose (Calif.) and Cary (N.C.), and subsidiaries in Hyderabad (India), Leeds and Kings Langley (UK), and Abu Dhabi (UAE). Job Title: Software Engineer II Location: Hyderabad, India Job Description: The compiler team at Blaize works on extending LLVM for Blaize’s needs along with developing compiler-based tooling for the wider Blaize SDK team. This candidate will be responsible for extending and improving LLVM and Clang for Blaize in areas such as OpenCL language extensions, IR code analysis, optimization development and addressing performance and correctness issues. The candidate will also establish and uphold stringent quality development and verification processes and standards in the development of highly dependable products that comply with all applicable requirements. Will ensure that the project is completed on time and meeting all the requirements. This candidate will also be responsible for stake holder engagement related to the function, delivery and support of the deliverables of compiler team at Blaize and successfully support the performance of the team. JOB RESPONSIBILITIES You will be responsible for identifying, prioritizing and executing tasks in the software development life cycle. You will have to collaborate with the internal teams and vendors to fix and improve the Blaize SDK. Ensuring the quality of our software releases through testing strategy of new features and changes. Understanding the requirements against sub-components and crucial features of the Blaize SDK. Developing comprehensive test plans, and collaborating with the automation team to ensure proper regression test coverage EDUCATION AND EXPERIENCE A bachelor’s degree in computer science. At least 3+ years of experience in software development One or more years of experience in compiler development preferred . One should have a strong knowledge of data structures, algorithms, and computer science fundamentals. Should have a strong knowledge of coding and good problem-solving skills. Experience with giving and receiving regular code review. REQUIRED KNOWLEDGE, SKILLS, AND ABILITIES Understanding of Computer architecture, graph processing and familiarity with assembly programming. Knowledge of traditional compiler optimization algorithms and parser construction is preferred Should have strong analytic and debugging skills Familiarity with AI/MLs is also beneficial. Knowledge of test automation tools and regression setup. C/C++ or Python based software verification experience. Blaize is an equal opportunity employer. We pride ourselves on having a diverse workforce and we do not discriminate against any employee or applicant because of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition, or any other basis protected by law. We respect the gender, gender identity and gender expression of our applicants and employees, and we honor requests for preferred pronouns. It is our policy to comply with all applicable national, state and local laws pertaining to nondiscrimination and equal opportunity.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Key Technical Skills Requirement Candidate should have deep and sound understating of: Memory basic design understating for different architectures Memory measurement parameters Memory timing/power characterization and compiler engine building with all accuracy parameters involved Memory power views All the LVF/different forms of variation parameter Memory lib w.r.t. parameters/arcs/SDF conditions/variation parameters/QA steps/different formats Different Simulator tools Should have thorough understanding of release process to customers Knowledge of scripting languages such as Shell, Perl Good working knowledge of MS excel, PPT Mentoring skills to Juniors Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075899 Show more Show less

Candidate required to have an interest in compiler, computer architecture, formal methods, security, or C++ programming. Show more Show less

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Hyderabad / Bangalore #LI-PK2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Permanent work from home is offered *Candidates who are well versed with French Language *Outstanding verbal & listening skills in English is must *Freshers are welcomed *Salary upto 10Lac PA *Rotational shifts *2 week offs Barkha @ 8851644223 Required Candidate profile Need only B2 Certified candidates *Any dropout/12th pass/UG & Graduate (Fresher & experienced) both can apply *Work from home *Telephonic Interview *Experienced candidates will have added advantage

Job Information Department Name Platforms & Compilers Job Type Full time Date Opened 25/04/2025 Industry Software Development Minimum Experience In Years 5 Maximum Experience In Years 10 City Chennai Province Tamil Nadu Country India Postal Code 600001 About Us MulticoreWare is a global software solutions & products company with its HQ in San Jose, CA, USA. With worldwide offices, it serves its clients and partners in North America, EMEA and APAC regions. Started by a group of researchers, MulticoreWare has grown to serve its clients and partners on HPC & Cloud computing, GPUs, Multicore & Multithread CPUS, DSPs, FPGAs and a variety of AI hardware accelerators. MulticoreWare was founded by a team of researchers that wanted a better way to program for heterogeneous architectures. With the advent of GPUs and the increasing prevalence of multi-core, multi-architecture platforms, our clients were struggling with the difficulties of using these platforms efficiently. We started as a boot-strapped services company and have since expanded our portfolio to span products and services related to compilers, machine learning, video codecs, image processing and augmented/virtual reality. Our hardware expertise has also expanded with our team; we now employ experts on HPC and Cloud Computing, GPUs, DSPs, FPGAs, and mobile and embedded platforms. We specialize in accelerating software and algorithms, so if your code targets a multi-core, heterogeneous platform, we can help. Job Description We are seeking a highly skilled and experienced Senior Compiler and Workload Performance Analyst. As a Senior Performance Analyst, you will play a pivotal role in analyzing and optimizing the performance of the compiler infrastructure and workloads. In addition, you will provide technical leadership, guidance, and mentorship to performance analysis teams. Your expertise in compiler technologies, workload analysis, and team leadership will drive the efficient and effective performance optimization of the target software systems. Responsibilities: Lead and mentor a team of performance analysts, providing technical guidance, support, and feedback to maximize individual and team performance. Conduct performance analysis and evaluation of the target compiler infrastructure, identifying bottlenecks and areas for optimization across various workloads and usage scenarios. Utilize advanced performance profiling and monitoring tools to gather and analyze performance data, identifying performance hotspots and areas of inefficiency. Develop and implement advanced performance optimization techniques, including algorithmic improvements, code transformations, and workload-specific optimizations. Lead workload analysis efforts, including workload modeling, characterization, and performance evaluation, to assess the performance impact on the compiler infrastructure. Generate comprehensive performance reports and documentation, presenting findings, recommendations, and optimization strategies to stakeholders in a clear and concise manner. Stay updated on the latest advancements in compiler technologies, workload analysis methodologies, and performance optimization techniques, driving innovation within the performance analysis teams. Qualifications: Bachelor's or Master's degree in Computer Science, Engineering, or a related field. Extensive experience as a Compiler and Workload Performance Analyst or in a similar role, with a strong track record in performance analysis and optimization. Experience in leading and mentoring teams, providing technical guidance, and fostering a collaborative and high-performance culture. In-depth expertise in compiler technologies, including compiler optimization techniques, code generation, and compiler internals. Proficiency in using performance profiling and monitoring tools to gather and analyze compiler and workload performance data. Strong knowledge of workload analysis methodologies, including workload modeling, characterization, and performance evaluation. Familiarity with programming languages such as C/C++, familiarity with LLVM or GCC compiler frameworks, and expertise in performance optimization at the compiler level. Solid understanding of computer architecture, hardware-software interactions, and workload-specific performance considerations. Strong analytical and problem-solving skills, with the ability to diagnose and resolve complex performance issues effectively. Attention to detail, a proactive mindset, and the ability to prioritize and manage multiple tasks and projects simultaneously

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience : Minimum 2 to 6 years of hands on experience in Synthesis and LEC Job Role Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Skill Set Proficiency in Python/Tcl Familiar with Synthesis tools (Fusion Compiler/Genus) , Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus Should be sincere, dedicated and willing to take up new challenges Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Overview We are looking for a Senior Software Engineer to help us build and evolve the core backend systems that power our next-generation tax platform. This role is ideal for someone who thrives at the intersection of high-scale backend engineering , and language runtime integration . You will work on the systems that underpin our business-critical tax calculation engines, contributing to the scalability, reliability, and performance of services that support critical tax logic execution. What you'll bring 6+ years of professional experience in backend or systems-level software development. Proven experience building scalable, distributed backend systems in production environments. Strong programming skills in Java, C# and/or C++. Low-level experience with JVM, CLR, or other language runtime environments. Solid understanding of performance optimization, multithreading, memory management, and networking. Experience with modern CI/CD pipelines, observability tools, and DevOps best practices. Preferred Qualifications Exposure to compiler or interpreter internals is a plus, but not required. Familiarity with containerized environments (Docker, Kubernetes) and cloud platforms. Knowledge of language tooling, custom DSLs, or domain-specific platforms is a bonus. Strong communication skills and a collaborative, growth-oriented mindset. How you will lead Design, build, and scale backend systems that support our tax development language and runtime. Contribute to the modernization and integration of legacy systems with modern runtimes (e.g., JVM, CLR). Implement performance-critical components using Java and C++ in a distributed, service-oriented architecture. Collaborate with compiler/runtime engineers and AI/ML teams to support intelligent language tooling. Ensure system reliability, observability, and operational excellence in production environments. Write clean, well-tested code and participate in design and code reviews. Mentor junior engineers and contribute to the technical growth of the team Show more Show less

IT Full-Time Job ID: DGC00684 Chennai, Tamil Nadu 3-5 Yrs ₹3.5 - ₹6.25 Yearly Job description Job Skills: Must have skills : Experience in designing and developing Web Apps using Java Spring Boot development, Core Java concepts around dependent technologies Expertise in building microservices Good understanding of EMS/NMS OOPs Concepts Design Patterns Clean understanding of Classes and Interfaces Generics, JVM and Memory Management, Caching Data into memory, Service Oriented Architecture, Concurrency (multithreading) Messaging Techniques, Complex Event Processing, Storage and Database Technologies (MongoDB, MySQL, ElasticSearch) Exposure to compiler like IDE OR ECLIPSE Value Add: Working experience with Dockers K8s Working knowledge on OSGI Knowledge on kafka, python, and ELK Good communication skills Scrum Master Problem solving skills You will play a key role in the overall estimation of work requirements to provide the right information on project estimations to Technology Leads and Project Managers. You would be a key contributor to building efficient programs/ systems and if you think you fit right in to help our clients navigate their next in their digital transformation journey.

Minimum qualifications: Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience. 2 years of experience in C++ and data structures and algorithms. 2 years of development experience in C++. Preferred qualifications: Master's degree or PhD in Electrical/Electronics Engineering, Computer Engineering, Computer Science, or a related field. Experience with Compilers. Experience in power and performance optimizations. Understanding of hardware, especially hardware that provides a high degree of parallelism. About The Job Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google’s needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. We are the team that builds Google Tensor, Google’s custom System-on-Chip (SoC) that powers the latest Pixel phones. Tensor makes transformative user experiences possible with the help of Machine Learning (ML) running on Tensor TPU. Our team’s work enables Gemini Nano, our efficient AI model for on-device tasks to run on Pixel phones. Our goal is to productize the latest ML innovations and research by delivering computing hardware and software. In this role, you will work on developing ML compilers for the Tensor TPU to accelerate Generative AI and other machine learning models running on custom hardware accelerators. You will also manage project priorities, deadlines, and deliverables. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Build compilers and tools that efficiently map ML models with a particular focus on computing use cases to the hardware Instruction Set Architecture (ISA). Evaluate various trade-offs of different parallelization strategies such as performance, power, energy and memory consumption. Collaborate with machine learning researchers to constantly improve the domain specific compiler. Collaborate with hardware engineers to evolve future accelerators. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form . Show more Show less

Candidate required to have an interest in compiler, architecture, formal methods, security, or C++ programming. Apply only if you have qualified for the GATE or any other equivalent exam and are willing to relocate to Roorkee. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary The engineer will be a part of cross geography team in developing maintainable, high-quality C/C++ code for an HDL language-based compiler and runtime support. Responsibilities include development of HDL compiler front-end for SV, improving compiler performance and infrastructure and flows. Exposure to RTL simulation/synthesis and runtime environment is highly desirable. Responsibilities Strong C/C++ development skills with a good understanding of object-oriented design. Strong background of computer science fundamentals (data structures, algorithms) Passionate to learn and explore new technologies and demonstrates good analysis and problem-solving skills. Good written and verbal communication skills, should be a quick learner and a team player. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Sr. Silicon Design Engineer Hyderabad, India Engineering 66192 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SE NIOR SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Hyderabad / Bangalore #LI-PK2 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS Silicon Design Engineer Bangalore, India Engineering 66143 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative Synthesis/PD/STA engineer to join our growing team. As a key contributor, you will be part of a team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and physical design in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects for the new features to be implemented in layout End-to-end RTL to GDS implementation of complex IPs and supporting the SOC customers Working with RTL team to resolve timing and congestion issues Build and develop methodology to converge multiple PNR blocks from RTL to GDS Analyze design metrics and make implementation choices to optimize PPA PREFERRED EXPERIENCE: ASIC design flow and direct experience with ASIC design in sub-7nm technology nodes Circuit timing/STA, and practical experience with Prime Time or equivalent tools Experience into various sign off flows like EMIR, physical verification, CDC Low power digital design and analysis Expertise in synthesis and physical design flows Modern SOC tools including Synopsys Fusion compiler, Primetime and Redhawk TCL, Perl, Python scripting Strong verbal and written communication skills Ability to organize and present complex technical information Fluent in working with Linux environment Mimimum 12 years of industry experience ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER The Role The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. Academic Credentials Qualification: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Hyderabad / Bangalore Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071102 Show more Show less

We're #hiring for a Founding GTM Engineer at Legacyleap ! We’re building Legacyleap, a GenAI platform that modernizes the legacy tech still powering critical infrastructure across banking, pharma, healthcare, and manufacturing. Think: ColdFusion. VB6. Classic ASP. EJB. .NET 4. The stuff nobody wants to touch but everybody depends on. Legacyleap automates the hardest parts of modernization: Code comprehension, translation, refactoring, testing, and deployment using a combination of Gen AI + compiler techniques. It’s already deployed in large enterprises, and the feedback has been incredible. In the last 4 months, we’ve done 70+ high-intent discovery calls with almost no outbound marketing. The demand is clear. The tech works. The team’s all-in. Now, we’re hiring our Founding GTM Engineer . What this role is: A high-trust, high-ownership GTM seat working directly with the CEO and technical founders Full support from a seasoned marketing team; you won’t be a lone wolf The chance to build the GTM engine from the ground up, not just "run" what’s already there What you'll do: Shape positioning and messaging across all GTM channels Build assets: emails, hooks, landing pages, decks, case studies, and more Drive early events, webinars, and partnerships Run growth experiments end-to-end and ship fast Own attribution, early rev ops, and pipeline clarity Get us in the room with CTOs, Heads of App Mod / Transformation, and Partners You might be right if: You've done $0 → $1M and/or $1M → $10M GTM for a deeptech or AI product You think in systems, write like a killer, and execute without waiting You understand enterprise buying journeys You care more about doing than managing You move fast, learn faster, and play for the team Location: Bangalore (Indiranagar) Team: Founding + Marketing Start date: 1-2 weeks Years of experience: Doesn’t matter. Show us you can do it. If this sounds like your kind of disruption, let’s talk. Apply here or reach out to shrey.nair@ideas2it.com. #GTM #FoundingRole #GenAI #ApplicationModernization #BangaloreJobs Show more Show less

Full Chip Physical Design Engineer Job Summary: We are seeking a highly motivated and skilled engineer to join our SoC implementation team. You will be responsible for the physical design of complex ASICs and SoCs, working on full-chip floorplanning, integration, and signoff activities to meet aggressive PPA (Power, Performance, Area) goals. Key Responsibilities: Drive full chip-level physical design flow from RTL to GDSII. Ownership of chip-level floorplanning, partitioning, and integration. Collaborate with RTL, synthesis, DFT, and STA teams to resolve cross-functional issues. Implement place & route flows including timing closure, IR/EM, and congestion optimization. Perform physical verification (LVS/DRC/ERC) and work with foundries to fix violations. Manage static timing analysis (STA) at top level and work closely with timing owners for signoff. Handle power planning and power domain implementation (UPF/CPF-based). Contribute to methodology improvements and automation. Required Qualifications: Bachelor's or Master’s degree in Electrical/Electronics/Computer Engineering or related field. 3–6 years of experience in physical design with at least one full chip tapeout. Hands-on expertise with industry-standard tools such as Synopsys (ICC2, Fusion Compiler, PrimeTime), Cadence (Innovus), and Mentor (Calibre). Strong knowledge of physical design concepts: floorplanning, CTS, routing, timing closure, IR drop, EM, DRC/LVS. Proficiency in scripting languages like Tcl, Perl, Python, or Shell. Familiarity with hierarchical design and ECO flows. Experience: 3 to 6 Years. Location: Bangalore / Hyderabad . Notice Period: Less than 30 days Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position: Principal Software Engineer Location: Noida Job Responsibilities The role’s day to day responsibilities cover: R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications BE/BTech/ME/MTech- Computer Science or others Experience: 10-15 Years Required Skills The successful candidate will possess the following combination of education and experience: Proficient in C/C++ Excellent programming and software engineering skills Experience With UNIX And/or LINUX Platforms Is Preferred RTL knowledge – System Verilog, VHDL is preferred Strong knowledge of Tcl is preferred Experience in language compiler Prior experience with large software development projects is highly recommended Prior experience with timing analysis software development projects is highly recommended Data structure and algorithmic skills We’re doing work that matters. Help us solve what others can’t. Show more Show less