Posted:1 week ago| Platform: Linkedin logo

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RTL Design Engineers

Key Responsibilities:

  • RTL design using Verilog/SystemVerilog for IP and SoC subsystems
  • Perform synthesis, linting, CDC/RDC analysis
  • Interface with verification, physical design, and architecture teams
  • Support SoC integration and debug
  • Ensure design quality and timing closure

Required Skills:

  • 2+ years of hands-on RTL design experience
  • Strong in digital design concepts (FSMs, pipelining, FIFOs)
  • Proficient with tools like Synopsys Design Compiler, SpyGlass, VCS
  • Experience with standard protocols (AXI, AHB, APB)
  • Basic scripting skills (TCL, Perl, Python)

How to Apply:

Nshalini.singh@einfochips.com

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