Analog Layout Engineer

Experience: 8+ Years

Location: Remote / India (must support USA/Canada time zone)

Travel: Willing to travel to the U.S. for project release (as required)

Job Title:

Location:

Experience Level:

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Role Overview

Senior Analog Layout Engineer

hands-on individual contributor role

robust, high-performance analog layouts

Key Responsibilities

• Lead the

  end-to-end schematic-to-layout design

  of high-speed analog and mixed-signal circuits.
• Perform

  floorplanning, pad-ring design, bump mapping

  , and

  ESD implementation

  at the chip level.
• Collaborate with

  SoC, circuit, and digital teams

  to ensure seamless layout integration and successful tape-out.
• Ensure layouts comply with all

  DRC, LVS, ERC, EM/IR, and reliability

  requirements.
• Optimize for

  matching, shielding, parasitic control

  , and high-speed signal integrity.
• Support

  simulation correlation

  and assist in debugging layout-related design issues.
• Take full ownership of assigned IP blocks and layout deliverables, driving them to completion with minimal supervision.

Required Skills & Expertise

• 8+ years

  of proven experience in

  Analog & Mixed-Signal Layout

  (preferably in high-speed converter or SerDes designs).
• Hands-on experience with

  TSMC 5nm FinFET technology

  and advanced

  layout optimization techniques

  .
• Strong understanding of

  chip-level planning, bump mapping

  , and

  ESD protection

  methodologies.
• Working knowledge of

  circuit simulation concepts

  — gain, bandwidth, noise, and linearity.
• Proficiency with industry-standard EDA tools such as

  Cadence Virtuoso

  ,

  Mentor Calibre

  , and

  Synopsys PVS

  .
• Excellent grasp of

  symmetry, matching, shielding, and low-parasitic design

  principles.
• Self-motivated, detail-oriented, and capable of working independently in

  cross-functional global teams

  .
• Willingness to

  work flexible hours

  (USA/Canada time zones) and

  travel internationally

  if required.

Preferred Qualifications

• Experience with

  PCIe

  ,

  GDDR

  , or other high-speed interface designs.
• Exposure to

  Chip-Package Co-Design (CPCD)

  and

  advanced ESD methodologies

  .
• Prior experience delivering

  product-level high-speed analog chips

  to production.

Why Join Us

• Work with cutting-edge

  5nm technology

  and world-class engineering teams.
• Be part of

  high-performance analog design projects

  shaping the future of connectivity and computing.
• Opportunity for

  global collaboration, technical leadership

  , and

  career growth

  .