Analog Layout Engineer

Project Role :

Analog Layout Engineer

Project Role Description :

Design the physical layout of analog circuits, ensuring proper component placement and routing for optimal performance. Address parasitic effects, signal integrity, and power distribution to meet design specifications. Collaborate to ensure the layout meets functional, electrical, and manufacturing requirements.

Must have skills :

Analog Layout

Good to have skills :

NA

Minimum 12 Year(s) Of Experience Is Required

Educational Qualification :

15 years full time educationSummary: As an Analog Layout Engineer, you will engage in the intricate process of designing the physical layout of analog circuits. A typical day involves ensuring optimal component placement and routing to enhance performance. You will address critical aspects such as parasitic effects, signal integrity, and power distribution, all while collaborating with various teams to ensure that the layout adheres to functional, electrical, and manufacturing specifications. Your role is pivotal in translating design concepts into tangible layouts that meet stringent requirements, fostering innovation and excellence in circuit design. Roles & Responsibilities: - Expected to be an SME. - Collaborate and manage the team to perform. - Responsible for team decisions. - Engage with multiple teams and contribute on key decisions. - Expected to provide solutions to problems that apply across multiple teams. - Facilitate knowledge sharing and mentorship within the team to enhance overall performance. - Continuously evaluate and improve layout design processes to increase efficiency and effectiveness. Professional & Technical Skills: - Must Have Skills: Proficiency in Analog Layout. - Working on layout design of owned blocks with Cadence Virtuoso XL. - Working on block and top-level level layout verification with Calibre. - Extensive PAD Ring and Top/Chip level layout experience - Working with analog/mixed-signal and digital design teams to ensure proper layout design o Block level floor planning and layout o IC top level floor planning and area estimation o Using recommended layout and verification techniques, tools, and flows to produce optimal designs o Generate post-layout extraction o Create layout related documentation and conduct layout reviews Preferably experience in TSMC, Finfet, SERDES/ADC/DAC/PLL - good to have but not mandatory. - Strong understanding of circuit design principles and methodologies. - Experience with layout tools such as Cadence or Mentor Graphics. - Familiarity with design rule checking and layout versus schematic verification. - Ability to analyze and mitigate parasitic effects in circuit layouts. Additional Information: - The candidate should have minimum 12 years of experience in Analog Layout. - This position is based at our Bengaluru office. - A 15 years full time education is required.