Analog Engineer- Layout

About the Company

Senior Analog Layout Engineer

About the Role

Analog Layout Engineer

Responsibilities

• Own end-to-end schematic-to-layout design for high-speed analog and mixed-signal circuits.
• Perform floor planning, bump and pad-ring design, and ESD implementation at the chip level.
• Collaborate with SoC, circuit, and digital design teams for layout integration and signoff.
• Ensure layouts meet all DRC, LVS, ERC, EM/IR and reliability standards.
• Handle layout matching, shielding, and parasitic optimization for high-speed performance.
• Support simulation correlation and assist in debugging layout-related circuit issues.
• Work independently, taking full ownership of assigned IPs and layout deliverables.

Qualifications

• 8+ years

  of hands-on experience in Analog & Mixed-Signal Layout, focusing on high-speed analog chips (High-Speed Converters).
• Proven expertise with TSMC 5nm FinFET technology and advanced layout techniques.
• Strong understanding of chip-level planning, bump mapping, and ESD design.
• Familiarity with simulation and circuit performance basics (gain, bandwidth, noise, etc.).
• Proficiency in Cadence Virtuoso, Calibre, and PVS.
• Excellent grasp of symmetry, matching, shielding, and low parasitic layout design.
• Ability to work independently and coordinate effectively with global teams.
• Flexibility to work in USA/Canada time zones and travel abroad if required.

Required Skills

• 8+ years of hands-on experience in Analog & Mixed-Signal Layout, focusing on high-speed analog chips (High-Speed Converters).
• Proven expertise with TSMC 5nm FinFET technology and advanced layout techniques.
• Strong understanding of chip-level planning, bump mapping, and ESD design.
• Familiarity with simulation and circuit performance basics (gain, bandwidth, noise, etc.).
• Proficiency in Cadence Virtuoso, Calibre, and PVS.
• Excellent grasp of symmetry, matching, shielding, and low parasitic layout design.
• Ability to work independently and coordinate effectively with global teams.
• Flexibility to work in USA/Canada time zones and travel abroad if required.

Preferred Skills

• Experience with PCIe & GDDR.
• Exposure to Chip-Package Co-Design (CPCD) and advanced ESD methodologies.
• Prior experience in product-level high-speed analog chip delivery.

Pay range and compensation package

Location: Remote / India (must support USA/Canada time zone)

Travel: Willing to travel to the U.S. for project release (as required)

Equal Opportunity Statement

We are committed to diversity and inclusivity.