VLSI Trainer(Physical Design / Design Verification)

1. Position: Physical Design (PD) Trainer / Mentor

Key Responsibilities

• Deliver comprehensive full-time courses, including lectures, labs, and project sessions.
• Prepare learners to be

  industry-ready

  by imparting practical and theoretical skills in Physical Design.
• Facilitate labs and projects in collaboration with lab instructors to ensure effective hands-on learning.
• Continuously update training materials, lab exercises, and projects to align with

  latest industry standards and technologies

  .
• Mentor students on

  technical communication, teamwork, and project collaboration skills

  .
• Manage course schedules, batch progress, and ensure smooth, efficient execution of all training activities.

For Candidates from Industry Background

• Experience:

  25 years in VLSI

  Physical Design

  , with proven tape-out experience in advanced nodes (7nm / 10nm / 14nm).

• Tools Expertise:

  Hands-on experience with

  Synopsys/Cadence/Mentor Graphics

  EDA tools.

• Skills:

  Strong understanding of

  Digital Design

  ,

  Verilog HDL

  , and

  CMOS fundamentals

  .

• Attributes:

  Self-motivated, proactive, and capable of driving tasks to completion independently.

• Leadership:

  Ability to

  mentor and guide junior engineers

  while collaborating effectively within a team.

For Candidates from Academic Background

• Experience:

  2-20 years in teaching or research in

  VLSI / Physical Design

  or related domains.

• Knowledge:

  Awareness of advanced technology nodes (7nm / 10nm / 14nm) and associated challenges.

• Tools Exposure:

  Familiarity with EDA tools (Synopsys, Cadence, Mentor Graphics).
• Candidates without prior hands-on experience will be provided training by ChipEdge to gain proficiency.

• Skills:

  Solid foundation in

  Digital Design

  ,

  Verilog HDL

  , and

  CMOS concepts

  .

• Attributes:

  Proactive learner, capable of independently managing deliverables and mentoring students effectively.

2. Position: Design Verification (DV) Trainer / Mentor

Key Responsibilities

• Deliver

  full-time Design Verification courses

  , including lectures, lab sessions, and project guidance.
• Prepare learners to be

  industry-ready

  by building strong skills in

  SystemVerilog (SV)

  ,

  UVM

  , and

  Digital Design concepts

  .
• Facilitate labs and project execution with support from lab instructors, ensuring hands-on learning.
• Regularly update course content, lab exercises, and projects to reflect

  latest verification methodologies and industry trends

  .
• Mentor students on

  technical communication, teamwork

  , and professional practices in project environments.
• Manage course schedules, batch timelines, and coordinate resources for smooth and efficient training delivery.

For Candidates from Industry Background

• Experience:

  25 years in

  Design Verification

  , with a valid

  Professional DV Certificate

  .

• Expertise:

  Strong proficiency in

  Verilog, SystemVerilog, UVM

  , and

  industry-standard verification methodologies

  .

• Tools Experience:

  Hands-on experience with

  EDA tools

  from

  Synopsys/ Cadence/

  Mentor Graphics

  .

• Protocols:

  Familiarity with standard bus and communication protocols used in the semiconductor industry.

• Technical Strengths:

  Good understanding of

  Digital Design

  ,

  Verilog HDL

  , and

  CMOS fundamentals

  .

• Attributes:

  Self-motivated, proactive, capable of driving projects independently, and mentoring junior engineers effectively.

For Candidates from Academic Background

• Experience:

  2-20 years of teaching or research experience in

  VLSI

  ,

  Digital Design

  , or

  Design Verification

  .

• Knowledge:

  Strong understanding of

  Digital Design

  ,

  Verilog HDL

  , and

  CMOS concepts

  .

• Tools Exposure:

  Awareness of EDA tools (Synopsys, Cadence, Mentor Graphics).
• Candidates without hands-on experience will be provided training by ChipEdge to gain tool proficiency.

• Attributes:

  Self-driven, quick learner, able to mentor students and collaborate effectively in a team-oriented environment.

Preferred Qualifications

• Prior

  academic teaching experience

  in

  VLSI Design / Verification

  .
• Minimum

  3+ years of relevant experience

  in Design Verification or related domains.

Why Join ChipEdge

• Opportunity to train and mentor aspiring

  VLSI Design Verification and Physical Design Engineers

  .
• Access to

  industry-grade tools and projects

  aligned with current semiconductor practices.
• Collaborative and growth-oriented environment focused on

  continuous learning and innovation

  .