2286 Verilog Jobs - Page 3

The ideal candidate for this position should have 1-2 years of experience in AMS design verification. You will be responsible for developing Verilog/VerilogA/VerilogAMS models for signal and power management modules to support top-level verification. Experience in full chip DV would be an added advantage. You will contribute to the development of the Full-Chip AMS-DV plan and own significant pieces of this verification process. It is essential to have the ability to drive best practices in the field of AMS-DV. In this role, you will work independently to identify bugs and resolve them formally with cross-functional teams. An understanding of analog power IPs will be beneficial as it can help in the debugging of chip-level AMS bugs. Proficiency in using tools such as Cadence Virtuoso, Spectre & Spice simulation, Incisive, and AMS simulators is required. You will utilize RTL and Gates+SDF, including process variation in back-annotated timing simulations. This will involve verifying chip-level timing between analog and digital circuits, parasitic resistance and capacitance, and using Assura parasitic extraction tools. Experience in constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus, is desired. The successful candidate should be able to work efficiently in a fast-paced product development environment. You will manage bug tracking and RTL code coverage, collaborate with design and systems teams to address bugs as they arise, and review digital and analog designs to provide guidance on Design for Verification architecture and features during chip development.,

You will be responsible for developing the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Additionally, you will participate in defining the architecture and microarchitecture features of the block being designed. You will apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals, as well as design integrity for physical implementation. It will be your responsibility to review the verification plan and implementation to ensure design features are verified correctly. You will also resolve and implement corrective measures for failing RTL tests to ensure the correctness of features. Providing support to SoC customers to ensure high-quality integration and verification of the IP block will also be a part of your role. Furthermore, you will drive quality assurance compliance for a smooth IP SoC handoff. Qualifications: - A Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience, or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience. - Expertise in microarchitecture, design, development, and integration of design blocks (IP) for system-on-chip (SoC) components. - Knowledge of power management is preferred, and experience with formal apps would be beneficial. - Expertise in Verilog and System Verilog-based logic design. - Experience in synthesis flow and timing closure, CDC, FEV. Knowledge of Python, Perl is a must. - Knowledge of considerations for performance, power, and cost optimization is desirable. - Knowledge of formal property verification using Jasper is preferred. - Demonstrate excellent self-motivation, communication, strong problem-solving, and teamwork skills. - Ability to set aggressive goals and meet/beat commitments. - Flexible enough to work in a dynamic environment and multitask seamlessly, with the ability to work independently and in a team. - Knowledge in IPs like I2C, I3C, SPI, UART, etc., is preferred. - Experience in the field of Dfx (ATPG coverage, SCAN insertion, VISA insertion, etc.) will be an added advantage. In this role, you will work within the Client Computing Group (CCG) at Intel, responsible for driving business strategy and product development for Intel's PC products and platforms. The CCG aims to deliver purposeful computing experiences that unlock people's potential, allowing each person to focus, create, and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. This role will be eligible for a hybrid work model, allowing employees to split their time between working on-site at their assigned Intel site and off-site. Please note that job posting details such as work model, location, or time type are subject to change. ,

As a SOC Performance Modeling Engineer at AMD, you will be an integral part of the Client Performance Modeling Team based in Hyderabad, India. Your primary responsibility will involve analyzing the architectural performance of notebook and desktop processors through modeling and RTL simulation. By collaborating with SoC, IP & Model architects, you will evaluate and debug CPU/GFX/NPU processor performance and suggest architectural enhancements to drive innovation. To excel in this role, you should possess a deep passion for cutting-edge SoC architecture, digital design, and verification. Your effective communication skills and ability to work seamlessly with architects & engineers across different locations and time zones will be crucial. Strong analytical and problem-solving abilities are essential, coupled with a willingness to learn and tackle challenges head-on. Key responsibilities in this role include developing architectural models, tools, and infrastructure, optimizing performance features, proposing enhancements for next-gen SOCs, conducting trade-off studies for performance, power, and area, evaluating benchmarks for various processors, advancing simulation infrastructure and methodology, and providing technical guidance to the Client SoC team. The ideal candidate would have 3-15 years of industry/academic experience, expertise in computer system simulation and performance evaluation, familiarity with ASIC HW design and verification languages/tools such as Verilog, System Verilog, System C, OVM/OVC, proficiency in programming and scripting languages like C/C++, Perl, Python, and a track record of analyzing system bottlenecks to optimize computing systems for performance. Additionally, detailed microarchitecture knowledge of CPU, GPU, NPU, I/O subsystem, and/or DRAM controller would be advantageous. An academic background in Computer/Electrical Engineering with a Bachelor's or Master's degree is required to qualify for this position at AMD. Explore the AMD benefits at a glance to discover the comprehensive perks offered to our valued employees.,

As a Senior Verification Engineer at NVIDIA's CPU verification team, you will have the exciting opportunity to work on cutting-edge CPUs that power the next generation of self-driving cars, including high-end SoCs like Xavier. Xavier features a custom "Denver" class CPU designed to deliver exceptional performance while meeting automotive standards such as ISO26262. In this role, you will collaborate with a team of talented engineers to verify micro-architecture and architecture features at various levels, ranging from unit to subsystem and full chip testbenches, including FPGA and Silicon. You will also have the chance to work closely with CPU architects to develop verifiable designs and contribute to full-stack development, ensuring that sequences are verified at the software simulator level and successfully implemented on silicon with a complete software stack. The ideal candidate for this position should have strong verification fundamentals and the ability to seamlessly transition between working on software simulators and silicon. Proficiency in CPU architecture, particularly ARM knowledge, as well as experience with Verilog, System Verilog, and excellent debugging skills are essential. Additionally, candidates should possess a minimum of 3 years of experience in Computer Science, Electronics Engineering, or related fields at the Bachelor's or Master's level. To truly stand out in this role, you should have experience working on diverse CPU unit/microarchitecture verification projects, demonstrate expertise in coverage-driven verification, and showcase a track record of successful collaboration with geographically diverse multi-functional teams. At NVIDIA, we offer competitive salaries, a comprehensive benefits package, and an inspiring work environment that attracts some of the most talented individuals in the industry. If you are a creative and autonomous engineer with a genuine passion for technology, we invite you to join our rapidly growing, best-in-class engineering teams and make a meaningful impact in the world of CPU verification.,

As an Applications Engineer at Lattice Semiconductor, you will be an integral part of the Boards design team within the Applications engineering organization. This role offers a dynamic environment where you will have ample opportunities to contribute, learn, and grow. Your primary responsibility will be to lead all aspects of PCB design for FPGA silicon products, starting from stack-up through production. This includes tasks such as PCB development, project management, architecture, schematic entry, layout/signal integrity analysis, and validation. You will collaborate closely with cross-functional teams to establish board specifications, meet design requirements, and adhere to constraints. Your expertise in microelectronic circuit design and hardware engineering will be essential in this role. Additionally, experience in PCB development, including planning, schematic entry (Allegro or equivalent), layout/signal integrity analysis, and validation is required. Hands-on lab experience, familiarity with physical interface standards, and FPGA development skills are highly desired. Proficiency in Verilog and/or VHDL, customer technical support, and silicon support are valuable assets for this position. Effective communication skills, both written and verbal, are crucial for collaborating with various teams and supporting customer interactions. You must be able to work independently as well as in a team environment, demonstrating strong analytical and problem-solving abilities. The ability to thrive in a fast-paced environment, prioritize tasks effectively, and manage competing priorities is essential for success in this role. At Lattice, we acknowledge that our employees are our most valuable asset, driving our success in a competitive global industry. We are committed to providing a comprehensive compensation and benefits program to attract, retain, motivate, reward, and celebrate top-tier employees. As an international developer of innovative low-cost, low-power programmable design solutions, Lattice values diversity, individuality, and the unique perspectives and ideas that each employee brings to the workplace. If you are passionate about working in a results-oriented environment, eager to achieve success within a team-oriented organization, and ready to thrive in a demanding yet supportive atmosphere, Lattice Semiconductor may be the perfect fit for you. Feel the energy at Lattice and join our global workforce in unlocking innovation and driving customer success.,

You will be part of a highly skilled and challenging high-speed parallel PHY design team, focusing on DDR, LPDDR, and other similar interfaces. Your responsibilities will include designing and developing high-speed interface PHY and its sub-blocks, such as data paths, analog calibration, training, IP initialization, low power control, test, and loopback. You will be involved in various aspects of design and verification from specification to silicon, including interface design for controllers and SoCs. Actively participate in problem-solving and implementing improvements, as well as mentoring and coaching other design team members on technical issues. Collaborate with Analog designers to ensure seamless interface between Digital and Analog circuits. You should possess a strong fundamental knowledge of digital design, Verilog, and scripting languages. Experience with micro-architecture, Asynchronous digital designs, Synthesis, STA, Lint & CDC, DDR/LPDDR JEDEC protocol, DDR PHY designs, training algorithms, data path designs, domain transfer designs, APB/JTAG, and DFI is required. A degree in M.S./M.Tech, BS/BE (Electronics) and a minimum of 7 years of experience are necessary for this role. Micron Technology is a global leader in memory and storage solutions, driving the transformation of information into intelligence. With a focus on customer satisfaction, technology leadership, and operational excellence, Micron offers a wide range of high-performance DRAM, NAND, and NOR memory and storage products through its Micron and Crucial brands. The innovations created by Micron's team enable advances in artificial intelligence and 5G applications, powering opportunities from data centers to the intelligent edge and enhancing the client and mobile user experience. For more information, please visit micron.com/careers. For assistance with the application process or requests for reasonable accommodations, please contact hrsupport_in@micron.com. Micron is committed to prohibiting the use of child labor and complying with all relevant laws, rules, regulations, and international labor standards.,

You are a talented and motivated Design Verification Engineer with 6-15 years of experience, sought by HCLTech VLSI division in Bangalore. Your role is crucial in ensuring the functionality and quality of next-generation integrated circuits. You will be working on challenging projects, utilizing your expertise in verification methodologies and tools. Your responsibilities will include developing and implementing verification plans using industry-standard methodologies like UVM. You will design and write robust verification environments to achieve high code coverage. Utilizing simulation tools such as ModelSim, Cadence Incisive, and Synopsys VCS, you will verify RTL functionality and debug verification failures to identify design issues" root cause. Collaboration with RTL design engineers to resolve bugs and ensure design revisions meet verification requirements is key. Your participation in code reviews and adherence to verification coding standards is essential, along with staying updated on the latest verification tools and methodologies. To qualify for this role, you should hold a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree is a plus). Your 6-15 years of experience in design verification for ASICs or SoCs, strong understanding of digital design principles, and proficiency in Verilog or VHDL with experience in methodologies like UVM are required. Experience with simulation tools and scripting languages like Python and Perl will be advantageous. Excellent analytical, problem-solving, communication, and collaboration skills are essential for effective team work. In return, HCLTech offers a competitive salary and benefits package, the opportunity to work on cutting-edge technologies and projects, a collaborative and dynamic work environment, and potential for professional development and career advancement. Thank you, Magenderan.R Manager - TAG HCLTECH,

You will be joining as a Senior FPGA Engineer professional at our Bangalore location with a minimum of 5 years of experience. In this role, your primary responsibilities will include collaborating with a team of product managers, developers, and testers to define feature requirements, developing feature specifications, and implementing detailed designs using Verilog and FPGA design tools. You will also be involved in problem isolation, fault finding in embedded systems, customer issue replication, and creating/updating release notes. Additionally, you will work closely with onsite and offsite development teams to deliver market-leading products globally and mentor junior engineers in development, code, and debugging. To excel in this role, you must be an expert Verilog/System Verilog developer with strong embedded debugging skills. Proficiency in AMD/Xilinx FPGA with Vivado/Vitis tool-chains for implementations and validation, as well as experience with Xilinx/AMD simulator/ModelSim for unit and system-level simulations, is essential. You should possess excellent analytical skills, adaptability to ambiguity and change, and a thorough understanding of the FPGA development cycle within project-based environments. Experience with modern 32-bit processors/microcontrollers like ARM, debuggers, protocol analyzers, and logic analyzers is required. Desirable skills include expertise in Embedded Linux Kernel and Device Drivers development, familiarity with video and audio codecs such as MPEG4 and JPEG, knowledge of USB protocols, and understanding of network protocol stack concepts like ethernet, IP, and TCP. Strong communication and documentation skills are necessary for this role. If you are interested in this opportunity, please share the following details along with your profile to vijitha.k@blackbox.com: - Total experience: - Relevant experience in FPGA: - Experience in Embedded: - Experience in Linux: - Current CTC: - Expected CTC: - Notice period: - Current Location: - Preferred Location: - Current Company: - Any pending offers: - Educational Qualifications,

You will be responsible for joining OnSemi's growing team in Bengaluru, India as a Sr. Principal Digital Design Engineer focused on New Product Development in Power Management. Your primary responsibilities will include working on the development of various Power Management products for consumer, industrial, and automotive applications such as DC-DC PMIC/POL, multiphase controllers, drivers, converters, LED drivers, SiC drivers, switches, and efuses. Your key responsibilities will involve collaborating with different product lines for RTL implementation of power convertor controller designs, working on digital design architecture, RTL, low power design, synthesis, and timing analysis. You will also interface with the Physical Design team for the power management chips using state-of-the-art RTL2GDS flows. As part of a large engineering team, you will collaborate effectively with design architects, digital verification, project management, and digital and analog design teams across various global locations. You will be involved in micro-architecture to RTL implementation, supporting system-level bring-up on pre-silicon platforms, and owning the technical outcome of Power Management ICs. Furthermore, you will be responsible for understanding project goals, executing with realistic schedules, reporting progress status, and supporting post-silicon validation activities. You will also lead and support customer issues, production issues, FW and system development, and failure analysis. Onsemi is a company driving disruptive innovations to create a better future, focusing on automotive and industrial end-markets. With a highly differentiated product portfolio, Onsemi aims to solve complex challenges and lead the way in creating a safer, cleaner, and smarter world. To qualify for this role, you should have a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate will possess a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages.,

You should have a minimum of 5 years of experience in developing FPGA-based prototype platforms. Your expertise should include proficiency with Xilinx (AMD) Vivado toolchain and implementation flow, as well as Synopsys/Mentor FPGA synthesis flow. It is essential to have a good understanding of Virtex-7, Virtex Ultrascale, and Virtex Ultrascale+ Architectures. In addition, you must be proficient in Verilog/System Verilog/VHDL and have a working knowledge of C/C++. Experience in using validation environment test equipment such as Logic Analyzers, Oscilloscope, Protocol Analyzers, etc. is required for this role. Having prior experience in working on ARM core architectures would be considered an advantage for this position.,

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, you enable customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, there is quite a lot to offer. Join a team that blurs the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow's idea - it is what we make real for our customers today. Siemens EDA, a global technology leader in Electronic Design Automation software, empowers companies worldwide to develop highly innovative electronic products faster and more efficiently. Siemens EDA's Questa Simulation Product is a core R&D team working on multiple verticals of Simulation. The team is characterized by its energy and enthusiasm, comprising motivated individuals based in Noida, with opportunities for travel to other locations in India and globally. As part of this team, you will contribute to impacting entire cities, countries, and the shape of things to come. Responsibilities: - Collaborate with a senior group of software engineers on core algorithmic advances and software design/architecture within the QuestaSim R&D team of Siemens EDA. - Contribute to final production level quality of new components and algorithms, as well as create new engines and support existent code. - Demonstrate self-motivation, self-discipline, and the ability to set personal goals, working consistently towards them in a dynamic environment to enhance your success. Required Experience: - A graduate with at least 2 years of relevant working experience and a degree in B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college. - Proficiency in C/C++, algorithm and data structures, Compiler Concepts and Optimizations. - Experience with UNIX and / or LINUX platforms is essential. - Basic Digital Electronics Concepts are a plus. - Knowledge of Verilog, System Verilog, VHDL, parallel algorithms, job distribution, ML/AI algorithms, and their implementation in data-driven tasks. - Exposure to Simulation or Formal based verification methodologies is beneficial. - Self-motivated, ability to work independently, guide others towards project completion, strong problem-solving, and analytical skills. Siemens is a collection of over 377,000 minds building the future, one day at a time in over 200 countries. The company is dedicated to equality, encouraging applications that reflect the diversity of the communities it works in. Employment decisions at Siemens are based on qualifications, merit, and business needs. Bring your curiosity and creativity to help shape tomorrow.,

You will be part of the Intel Core Design Team driving Intel's latest CPUs in the world's leading process technologies. As a Pre-Silicon Verification Engineer, you will develop pre-Silicon functional verification tests to ensure that the system meets design requirements. Your responsibilities will include creating test plans for RTL validation, defining and running system simulation models, and implementing corrective measures for failing RTL tests. You will also analyze results to modify test benches and tests to improve validation plans. As a Pre-Silicon Verification Lead/Architect, you will lead and guide a team to develop complex pre-Silicon verification environments, verification components, and coverage plans. You will drive strategic initiatives related to tools, methodologies, and quality to reduce the overall cycle time of validation projects. Working closely with hardware architects and logic designers, you will influence SoC and system design to ensure product success. Additionally, you will provide technical leadership, manage resources, and drive engineering activities to meet schedules, standards, and cost. To qualify for this role, you must possess a master's degree in Electronics or Computer Engineering with at least 4 years of experience or a Bachelor's Degree with at least 10 years of experience in Pre-Silicon Verification Environment. Preferred qualifications include experience with RTL design, Verilog, System Verilog based verification techniques, CPU architecture/Processor Verification, Perl/Python, Linux OS, SVTB UVM, or Specman (e). You should be a team player with excellent self-motivation, communication, problem-solving, and teamwork skills. The Client Computing Group (CCG) at Intel is responsible for driving business strategy and product development for PC products and platforms. As part of this group, you will contribute to delivering purposeful computing experiences that unlock people's potential. This role is an Experienced Hire position based in India, Bangalore, and eligible for a hybrid work model that allows splitting time between on-site and off-site work.,

As an experienced professional in ASIC development with a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, you will be leading a team of engineers in Bengaluru to deliver AI/ML compute intensive IPs and subsystems. With 8 years of experience in Verilog/SystemVerilog, VHDL, or Chisel, and 4 years of people management expertise, you will collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. Your responsibilities will include taking ownership of complex IPs or subsystems, implementing RTL, and driving design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Additionally, you will be tasked with identifying and driving power, performance, and area improvements for the domains owned. Your role will involve working on cutting-edge SoCs used to accelerate machine learning computation in data centers. You will be solving technical issues with innovative micro-architecture and practical logic solutions, and evaluating design options with complexity, performance, power, and area in mind. Furthermore, you will contribute to the innovation behind products loved by millions worldwide, leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The future of AI/ML hardware acceleration awaits you in this role, where you will have the opportunity to shape cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You will be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. Your contributions will play a crucial role in delivering high-quality designs for next-generation data center accelerators, collaborating with various teams such as architecture, verification, power and performance, and physical design. The Technical Infrastructure team at Google is responsible for the architecture that keeps everything running smoothly online. From data centers to the next generation of Google platforms, this team ensures Google's product portfolio remains at the forefront of innovation. By joining this team, you will play a key role in maintaining networks, ensuring users have the best and fastest experience possible.,

We are seeking an experienced RTL Design Engineer to be a part of our advanced ASIC/SoC development team in Bengaluru. As an RTL Design Engineer, you will be responsible for developing high-quality, synthesizable RTL code using Verilog/SystemVerilog and integrating complex IPs and subsystems into high-performance SoCs. Collaboration with system architects, contribution to micro-architecture, and ensuring design quality through checks like Lint, CDC, and Synthesis will be key aspects of this role. Your responsibilities will include leading SoC-level integration activities, providing technical guidance in design reviews, and interfacing with cross-functional teams for smooth bring-up and signoff processes. The ideal candidate should possess a Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering, along with at least 7 years of experience in RTL design and SoC integration. Strong skills in Verilog/SystemVerilog, knowledge of SoC architecture and bus protocols, and proficiency in industry tools like Design Compiler, Spyglass, and VCS are essential for this role. If you have a deep understanding of clock/reset strategies, hierarchical design practices, timing closure, synthesis flows, and constraints development, along with strong analytical and debugging skills to resolve complex RTL and integration issues, we would like to hear from you. Join us and contribute to the design, integration, and verification of cutting-edge IPs and subsystems within high-performance SoCs.,

As an Electrical Engineer or Computer Science professional with a Bachelor's degree and 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon, you will have the opportunity to contribute to the innovation behind Google's direct-to-consumer products. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Your responsibilities will include defining the microarchitecture of IPs, Subsystems, or SOCs, working with cross-functional teams to ensure quality, schedule compliance, and PPA optimized design. You will collaborate with Verification, Design for Test, Physical Design, and Software teams to make design decisions and represent project status throughout the development process. Additionally, you will define block-level design documents such as interface protocols, block diagrams, transaction flows, and pipelines. You will be responsible for RTL coding for SS/SOC integration, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Working with key design collaterals such as SDC and UPF, you will negotiate the right collateral quality and identify solutions in collaboration with stakeholders. Preferred qualifications include a Master's degree or PhD in Electrical Engineering or equivalent practical experience, experience with chip design flow and cross-domain involving DV, DFT, Physical Design, and software. Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip-level verification will be advantageous. Knowledge in areas such as Processor Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin-muxing is also beneficial. Join a team that pushes boundaries and works towards developing custom silicon solutions that power the future of Google's products, loved by millions worldwide. Contribute your skills and expertise to create radically helpful experiences by combining the best of Google AI, Software, and Hardware. Be a part of a team that aims to make people's lives better through technology.,

You are a highly experienced ASIC RTL Design Architect responsible for leading the design and verification of cutting-edge SoCs and high-speed digital IPs. With over 10 years of experience in ASIC/FPGA design, your expertise lies in RTL using Verilog/SystemVerilog, Lint, CDC, and Spyglass-based design verification methodologies. Your main responsibilities include leading RTL design and micro-architecture for high-performance ASIC SoCs, ensuring compliance with Lint, CDC, and SDC constraints using Spyglass or equivalent tools, driving design optimization and timing closure, as well as collaborating with cross-functional teams such as Design Verification, DFT, Physical Design, and Software teams. You will also be involved in developing and reviewing architecture specifications, coding guidelines, and best practices, as well as performing synthesis, timing analysis, and static verification using tools like STA, LEC, and Formal Verification. Key requirements for this role include a minimum of 10 years of experience in ASIC RTL design and architecture, expertise in Verilog/SystemVerilog for RTL design, strong knowledge of Spyglass Lint/CDC and static verification methodologies, experience in SoC micro-architecture, high-speed interfaces, and power optimization. Additionally, you should have a solid understanding of synthesis, STA, timing closure, backend constraints, experience with EDA tools like Synopsys, Cadence, Mentor Graphics, and familiarity with UVM-based verification and scripting languages such as TCL, Python, or Perl. Preferred qualifications include an M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, or related field, experience in chip tape-out and production silicon, and an understanding of hardware security, reliability, and safety standards. If you are looking to be part of a team that is shaping the future of high-performance computing, apply now and join us in building innovative solutions together.,

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions to power Google's direct-to-consumer products. Your role will involve contributing to the innovation that drives the creation of products loved by millions worldwide, shaping the next generation of hardware experiences for unparalleled performance, efficiency, and integration. Your responsibilities will include: - Contributing as an ASIC RTL engineer to sub-system and chip-level integration activities. This will involve task planning, conducting code and design reviews, and contributing to sub-system/chip-level integration. - Working closely with the architecture team to develop implementation strategies that meet quality, schedule, and power performance area requirements for sub-system/chip-level integration. - Collaborating with the subsystem team to plan SOC milestones, quality checks, and guide subsystem teams with SOC level requirements such as IPXACT, CSR, Lint, CDC, SDC, UPF, etc. - Engaging with a cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and provide project status updates throughout the development process. To be successful in this role, you should have a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. You should also have at least 3 years of experience in RTL coding using Verilog or SystemVerilog language, with experience in high-performance design, multi-power domains with clocking. Preferred qualifications include experience with multiple SoCs with silicon success, knowledge of ASIC design methodologies for front quality checks, and domain expertise in areas such as Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, PinMux. Additionally, an understanding of cross-domain activities involving domain validation, design for testing, physical design, and software will be beneficial. Join us at Google and be part of a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. Help us research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to make people's lives better through technology.,

You will be part of ACE India, in the P-Core design team driving Intel's latest CPUs in the latest process technology. As a member of the team, you will lead the design analysis and methodologies of various memory blocks, ensuring they meet over 5GHz frequency and low-power digital designs with optimal area utilization. Your role will involve a deep understanding of different memory design concepts such as SRAM, RF, and ROM along with expertise in static timing analysis concepts. Close collaboration with Layout and Floor planning teams will be essential for successful back end design implementation of new features. Additionally, you will specialize in memory post-silicon analysis and possess a good grasp of statistical variation. To qualify for this position, you must hold a master's degree in electrical or computer engineering with a minimum of 8 years of experience in the related field. Alternatively, a bachelor's degree with at least 10 years of experience will be considered. Technical expertise in synthesis, P and R tools is preferred for this role. Preferred qualifications include experience in digital design with a focus on high speed and low power, familiarity with Verilog/VHDL, and proficiency in Tcl, Perl, and Python scripting. A good understanding of spice simulations and analysis, custom circuit design, IO design, full chip clocking, and strong verbal and written communication skills are also desired. Previous experience in design and verification of high-speed clocks, hierarchical designs, and budgeting of latencies and skews will be beneficial. This role falls under the Experienced Hire category and is based in India, Bangalore. The Client Computing Group (CCG), responsible for driving business strategy and product development for Intel's PC products, is the primary business group for this position. CCG focuses on delivering purposeful computing experiences across various form factors such as notebooks, desktops, 2 in 1s, and all in ones, aiming to unlock people's potential through innovative products. The role will involve collaborating with industry partners to design and deliver a predictable cadence of leadership products, contributing to Intel's mission of enriching the lives of every person on earth. This role will be eligible for a hybrid work model, allowing employees to split their time between working on-site at the assigned Intel site and off-site. Please note that job posting details such as work model, location, or time type are subject to change.,

About Newton School Come be part of a rocket ship that’s creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates. We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CRED’s Kunal Shah, Flipkart’s Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built—from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. 4 - 7 years of experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: ○ Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. ○ VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats.

About Newton School Come be part of a rocket ship that’s creating a massive impact in the world of education! On one side you have over a million college graduates every year with barely 5% employability rates and on the other side, there are thousands of companies struggling to find talent. Newton School aims to bridge this massive gap through its personalized learning platform. We are building an online university and solving the deep problem of the employability of graduates.We have a strong core team consisting of alumni from IITs and IIM, having several years of industry experience in companies like Unacademy, Inmobi, Ola, and Microsoft - among others. On this mission, we are backed by some of the most respected investors around the world, - RTP Global, Nexus Venture Partners, and a slew of angel investors including CRED’s Kunal Shah, Flipkart’s Kalyan Krishnamoorthy, Unacademy and Razorpay founders, Udaan’s Sujeet Kumar among others. About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities Teach Computer Architecture by drawing from real-world VLSI design experience covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes Must-Have Skills & Qualifications B.Tech / M.Tech / Ph.D. in Computer Engineering, Electronics, Electrical, or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: ○ Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. ○ VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence, ModelSim, Synopsys, Xilinx, Mentor Graphics, etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting (Tcl, Shell, Python). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V, ARM-based processors, SoC Design, or low-power systems Exposure to DFT, verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats.

Objectives of this role Design and develop hardware products, including circuit boards, components, and systems, while adhering to industry standards and best practices. Generate and maintain hardware design, testing, and quality control documentation. Participate in design reviews, risk assessments, and product validation activities to ensure compliance with regulations. Collaborate with cross-functional teams, including design, development and customer support, to provide feedback and input on product design, performance optimisation, and manufacturability. Your tasks Conduct thorough testing and validation of hardware products to ensure compliance with specifications, requirements and quality standards. Perform root cause analysis and troubleshooting of hardware defects and implement preventive measures for malfunctions to minimise future occurrences. Stay up to date with the latest advancements in hardware testing methodologies and apply them to improve the overall quality of our products. Required skills and qualifications Bachelors degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of demonstrable experience as a computer hardware engineer. Strong knowledge of hardware design principles, testing tools, equipment, and techniques (mainly PCB designing). Excellent analytical and problem-solving skills with an eye for detail and precision. Ability to work independently and manage multiple tasks simultaneously. Preferred skills and qualifications Proficiency in programming languages, like C/C++ and/or Verilog/VHDL. Familiar with industry regulations in India, like ISO 9001, ISO 13485, BIS and RoHS. Knowledge of hardware regulatory requirements, such as FCC and CE. Strong communication, teamwork, and project management skills. Any Degree in Electronics and communication, BEEE, Mtech

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

Learn everything about RISC-V ISA and its extensions. Build reusable test libararies and test suites for compliance testing. Required Skill Set Must have good knowledge of python scripting Basic computer architecture knowledge. Good to have experience with FPGAs, RISC-V ISA

Challenging and Interesting work on building and enhancing Indias only completely open-source RISC-V based SHAKTI processors. Learn everything about the entire flow from spec to silicon. Work on state-of-the-art research topics and engineering efforts. Exposure to engage with foreign universities and support in preparation to pursue higher studies in India/Abroad. Exposure to engage with leading industry partners thereby improving your career trajectory and exposure. International Publications can also be achieved as part of tenure, boosting your research potential for higher studies. Required Skill Set Must have basic expertise in at least one of: verilog, vhdl, bluespec system verilog and/or chisel. Must have knowledge: digital design, pipelining Basic computer architecture knowledge, include one or more of : in-order cores, out-of-order cores, processors, caches, SoC development, memory architecture, etc. Good to have experience with FPGAs , performance modelling, workload analysis/benchmarking, python scripting, knowledge of peripheral and communication IPs

•BE/B.Tech in ECE /M.Tech in VLSI with 6 to 9 years experience in Analog Mixed Signal Verification •Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks •Very Good experience in Analog Mixed Signal verification simulation tools •Good experience in System Verilog, UVM methodologies •Able to train the team members and guide them to the solutions for problems •Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch. •Good experience in Gate level netlist simulation •Experience in Python, Perl, Shell scripting is added advantage. •Good communication and documentation skills