2286 Verilog Jobs - Page 4

Roles & Responsibilities: Product design involving electronic systems, subsystems, cards and assemblies; Hands-on Analog and Digital Circuit design involving components like Operational Amplifiers, transistors, Micro-controller, FPGA etc; Integrating various types of sensors using analog and digital interfaces like RS232/422/485, ADC etc. to customs/COTS hardware. Understanding customer requirement and developing a solution meeting that requirement. Complete documentation covering functional, technical and design aspects. Coordination with, and Management of, other stakeholders like PCB designers, mechanical engineers, firmware engineers, sourcing team, testers, etc; Development of prototypes; Preparation of Design, Manufacturing and Repair Documentation; Developing Test jigs & Fixtures Requirements: Candidate have expertise and at least 2 years experience in Analog and Digital Circuit design involving components like Micro-controllers, Operational Amplifiers, switches, transistors, transformers, FPGA etc; Must have experience in an electronics product industry, like Defence, Telecom, railway electronics/ signaling etc., Candidates from industries like automotive, consumer durables, contract manufacturing will not be suitable Educational Qualification: B.E./B.Tech/ M.Tech in Electronics/Communications with minimum 65% marks Must be willing to relocate to company R&D centre at Mohali; Job will involve travel to client locations if required Note: Exp. in Schematic entry/PCB design are NOT required Exp. In VHDL/Verilog/Chip Design are NOT required Job Types: Full-time, Permanent Pay: ₹800,000.00 - ₹1,200,000.00 per year Benefits: Provident Fund Schedule: Day shift Supplemental Pay: Performance bonus Experience: Product Design: 2 years (Preferred) Digital Circuit design: 2 years (Preferred) Work Location: In person

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Looking for Siemens EDA ambassadors We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us – whichever path you take, we’re looking forward to seeing your point of view! Veloce Transactors (Accelerated Verification IPs) Veloce Transactor Group is part of Mentor Emulation Division R&D located in Noida. Group develops transactors (RTL based IPs/VIPs) for various protocol solutions in Networking, Display, Storage, Mobile, Automobile etc. At present Veloce Transactor Library supports more than 25 protocol solution and growing further. This is your Role Individual will be responsible for developing transactor (xVIP) solutions for CCIX or PCIe based interconnect technology. Primary responsibilities include understanding standard specifications, develop architecture and micro-arch for the design and writing a synthesized design using Verilog/System Verilog. Required Experience: We seek a graduate with at 5-8 years of relevant working experience with (BE/BTech/ME/MTech/MS) from a reputed engineering college. We value your experience on the protocol e.g. PCIe, USB, Ethernet, AMBA in Design or Verification. Good understanding of IP Verification Methodologies, Verification procedures and practices are plus! Experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc We value expertise in Verilog, SystemVerilog, and SystemC, as well as experience in developing RTL for FPGAs, ASICs, and IPs, as this will greatly contribute to the quality of our products. We expect candidates to be able to build verification test plans and environments, develop test cases, utilize VIPs, and efficiently debug defects identified during verification processes. We consider exposure to object-oriented programming languages like C++ an advantage, and experience in scripting languages such as Perl will also be valuable in automating tasks and improving efficiency. You need to engage with customers for Deployment and R&D assistance. We've got quite to offer, how about you? We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. #LI-EDA

Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. In this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for sub-systems and the full chip. You will participate in the design verification and bring-up of the chip and subsystems by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team. You will participate in the lab bring-up of these blocks either in FPGA, emulation, or silicon by potentially writing test scripts, analyzing lab data, proposing experiments, etc. Role You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will: Design world class hardware and software Communicate and work with team members across multiple disciplines Deliver detailed test plans for verification of the full chip or sub-system by working with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write tests in C to run out of the CPU Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Participate in test plan and coverage reviews The ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages and verification methodologies. They should have experience verifying complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues. Key job responsibilities Design Verification of Subsystems such as CPU, NPU, and SOC. Drive Verification Methodology using System Verilog / C++ based test benches. Basic Qualifications Bachelor’s degree or higher in EE, CE, or CS 10+ years or more of practical semiconductor design verification experience including System Verilog, UVM, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, FPGA, emulator, software environments and system testing Experience defining verification methodologies Experience with test plan development, building the necessary test bench infrastructure, developing tests and verifying the design Experience with writing directed tests Experience identifying bugs in architecture, algorithms, functionality and performance with strong overall debug skills Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing Experience with industry standard tools and scripting languages (Python or Perl) for automation Understanding and knowledge of object oriented programming concepts Preferred Qualifications PhD in Computer Science, Electrical Engineering, or related field Experience with ARM and various DSP ISA Experience with CPU block level testing Experience debug Company - Amazon.com Services LLC Job ID: A3016320

Description The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa We want you to help us build on the success of our first generation of ML accelerator at edge, Work hard Have fun Make history, We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production, As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability from early DFT architecture planning to high-volume silicon bring-up and yield ramp, Lead development & implementation of DFT architecture including system level DFT for a full chip Write and guide others in writing design flow and project documentation, Own DFT planning, milestone tracking, and cross-functional checklist reviews, Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists, Review and sign-off SoC level DFT mode timing closure using static timing analysis Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon Keep informed on and introduce new technology into Design-for-Test process as appropriate, Education BASIC QUALIFICATIONS BS/BE or MS/ME in Electrical Engineering, Computer Engineering, or related field, Experience 15+ years in SoC/ASIC DFT, including 3+ years Leading DFT, Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production, DFT Architecture Expertise Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including: Scan architecture, compression, and ATPG implementation for high fault coverage and test quality, MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration, IEEE 1149 x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures, DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths, RTL and gate-level debug, including mismatch triage and simulation correlation, Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation, Tool Proficiency Deep hands-on experience with Tessent / Industry Std EDA tools, including: IJTAG ICL extraction and PDL modeling, DFT logic insertion, pattern generation, and diagnostics, Design Background Experience in writing verilog/system verilog RTL related to DFT logic design, ATE Test Readiness Lead DFT-to-ATE handoff, including: Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets, Pattern validation, format conversion, and debugging across wafer sort and final test, Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements, Silicon Debug Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis, Automation Skills Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl, Collaboration Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing, Execution Excellence Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success, Leadership PREFERRED QUALIFICATIONS Led multi-site/global DFT teams, mentoring engineers and managing design reviews, Drove design-for-test planning in collaboration with customers or design services partners, Technical Depth Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies, Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues, Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement, Our inclusive culture empowers Amazonians to deliver the best results for our customers If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, amazon jobs / content / en / how-we-hire / accommodations for more information If the country/region youre applying in isnt listed, please contact your Recruiting Partner, Company ADCI BLR 14 SEZ Job ID: A3037331 Show

#Urgent_Opening_for Canvendor #Hiring: DV Engineer (10+ Years Experience) | Pune| Immediate Joiners Preferred Location: Pune, India Experience: 10+ Years Notice period: Immediate to 30days Skills Highlighted: Key Requirements: -Bachelor’s degree or above in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines, with 10 years of experience. -Understanding of SoC architecture and functionality -Understanding of directed and constrained random verification methodology -Good knowledge in UVM, Verilog, System Verilog, C/C++, Shell -Good software programming skills are important therefore -Good knowledge in Scripting like Perl, TCL or Python is a plus -Good communication skills to interact with teams across the globe and work independently If interested kindly share your updated CV to anushab@canvendor.com

Roles & Responsibilities: Product design involving electronic systems, subsystems, cards and assemblies; Hands-on Analog and Digital Circuit design involving components like Operational Amplifiers, transistors, Micro-controller, FPGA etc; Integrating various types of sensors using analog and digital interfaces like RS232/422/485, ADC etc. to customs/COTS hardware. Understanding customer requirement and developing a solution meeting that requirement. Complete documentation covering functional, technical and design aspects. Coordination with, and Management of, other stakeholders like PCB designers, mechanical engineers, firmware engineers, sourcing team, testers, etc; Development of prototypes; Preparation of Design, Manufacturing and Repair Documentation; Developing Test jigs & Fixtures Requirements: Candidate have expertise and at least 2 years experience in Analog and Digital Circuit design involving components like Micro-controllers, Operational Amplifiers, switches, transistors, transformers, FPGA etc; Must have experience in an electronics product industry, like Defence, Telecom, railway electronics/ signaling etc., Candidates from industries like automotive, consumer durables, contract manufacturing will not be suitable Educational Qualification: B.E./B.Tech/ M.Tech in Electronics/Communications with minimum 65% marks Must be willing to relocate to company R&D centre at Mohali; Job will involve travel to client locations if required Note: Exp. in Schematic entry/PCB design are NOT required Exp. In VHDL/Verilog/Chip Design are NOT required Job Types: Full-time, Permanent Pay: ₹800,000.00 - ₹1,200,000.00 per year Benefits: Provident Fund

You will be involved in the design and development of Packet Radio baseband using VHDL/Verilog. Your responsibilities will include working on Channel Coding & FEC and implementing direct conversion, modulation/demodulation techniques including burst modems (xPSK, xQAM). Experience in Channel equalization MIMO will be essential for this role. As a qualified candidate with a B.Tech (ECE) / M.Tech degree and 4 to 5 years of experience, you will have the opportunity to showcase your skills in Baseband (Including DSP) Design Using FPGA (Modem Design). This position offers a chance to work on global projects in the energy sector and make a significant impact. If you are seeking a challenging role that encourages innovation and expertise building, then this opportunity is perfect for you. Join us and be a part of a dynamic team where your growth and development are prioritized. To apply for this position, please send your resume to jobs@icommtele.com. We are currently looking to fill 1 open position.,

As a Lead Verification Engineer with over 7 years of experience, you will be an integral part of a geographically distributed verification team working on next-generation ASIC and FPGAs. Your responsibilities will include developing testplans, implementing testbenches, creating testcases, and ensuring functional coverage closure. Additionally, you will handle regression testing, contribute to verification infrastructure development, and develop both directed and random verification tests. In this role, you will be expected to debug test failures, identify root causes, and collaborate with RTL and firmware engineers to resolve design defects and test issues. You will also review functional and code coverage metrics, modify or add tests, and constrain random tests to meet coverage requirements. Furthermore, you will collaborate closely with design, software, and architecture teams to verify the design under test. The preferred experience for this role includes proficiency in IP-level FPGA and ASIC verification, knowledge of protocols such as PCIe, CXL, or other IO protocols, and proficiency in Verilog/SystemVerilog and scripting languages like Perl or Python. Hands-on experience with SystemVerilog and UVM is mandatory, along with experience in developing UVM-based verification testbenches, processes, and flows. A solid understanding of design flow, verification methodology, and general computational logic design and verification is also essential. About the Company: ACL Digital, a leader in digital engineering and transformation and part of the ALTEN Group, empowers organizations to thrive in an AI-first world. With expertise spanning the entire technology stack and seamlessly integrating AI and data-driven solutions from Chip to cloud, ACL Digital offers a strategic advantage in navigating the complexities of digital transformation. Join us at ACL Digital and be a part of shaping the future as our trusted partner.,

The Core Switch Group (CSG) at Broadcom, the industry leader in cutting-edge networking ASICs, is known for developing advanced protocols and delivering unmatched port density and bandwidth performance. Our team has contributed to iconic switching solutions like the Trident and Tomahawk series, setting benchmarks in the networking world. Broadcom, a global innovator in fabless communications semiconductors, software, and systems, is proud to be recognized as one of Fortune magazine's "Most Admired Companies." We foster a culture that embraces change, values risk-taking, and thrives on tackling the impossible. At Broadcom, we reward innovation and initiative with competitive salaries, industry-leading benefits, and opportunities for growth in an open, collaborative work environment. If you're a passionate engineer eager to shape the future of networking, Broadcom is where you can outdo, outsmart, and outperform. Join us and make an impact! Key Responsibilities: - Conduct detailed studies of chip architecture and micro-architecture to define, develop, and execute comprehensive test plans that thoroughly validate switch features in both emulation phase and post-silicon. - Develop system-level tests using Tcl, ITcl, Python, C/C++ to verify networking switch chips and systems. - Build and Synthesize Verilog based models for emulation platforms such as Zebu or Palladium. - Debugging Expertise: Perform chip/system-level debugging and root cause analysis for hardware and software issues, effectively addressing Pre/Post Silicon issues and challenges. - Automation and Methodology: Develop and optimize automation scripts and emulation methodologies to enhance efficiency, reusability, and value. - Reusable Components: Create reusable synthesizable design blocks, libraries, and verification components to streamline emulation processes. - Silicon Bring-up: Plan, organize, and execute silicon bring-up and test plans. - Environment Management: Create and maintain robust emulation and post-silicon validation environments, supporting a global user community. - Cross-functional Collaboration: Collaborate with Architecture, Micro-Architecture, Design, DV, Software, and other teams to achieve thorough emulation coverage and smooth project execution. What You Bring: - Bachelors with 12+ years in emulation or post-silicon validation of networking ASICs. - Expertise in Verilog/SystemVerilog, C/C++, Tcl, Python, and scripting for automation. - Hands-on experience with emulation platforms (Zebu, Palladium), traffic generators (IXIA, Spirent), and interface protocols (PCIe) is desirable. - Strong debugging skills and familiarity with DPI transactors, assertions, and coverage-driven verification. - Excellent communicator who thrives in a collaborative, fast-paced environment.,

DV: Experience: 4+years of Experience General verification expertise – System Verilog. UVM Understanding of ARM processor based SOCs, AXI / AHB Good knowledge of Processor based C tests for SOC verification (test coding, compilation, loading in TB, failure debug) Strong hands on work experience of test development, simulation along with usage of popular EDA tools Good debug skills – Check that engineer has done reasonable amount of debug in past projects Has logical and methodical approach to debug issues /failures Has used standard tools for debugging, as applicable

You have an exciting opportunity to join a dynamic team at MarvyLogic in Bengaluru/Bangalore. With over 10 years of experience in ASIC RTL Design and a Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus), you will be a valuable addition to our team. As a member of our team, you will be responsible for various tasks related to ASIC RTL Design. Your expertise in Verilog/System Verilog proficiency, experience with multiple clock and power domains, and integration and validation of high-speed PCIe IP core will be crucial. You will also need familiarity with PCIe protocol analyzers and debug, as well as PCIe driver and application software for Linux/Windows. Your role will involve RTL Design and implementation of interface logic between PCIe controller and DMA engines for high-performance networking applications. You will be creating block-level micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance throughout the design flow. In addition to your technical responsibilities, you will also need to work and communicate effectively with multi-site teams. Your experience in ASIC product life cycle, including requirements, design, implementation, test, and post-silicon validation, will be essential in this role. If you are passionate about technology solutions and enjoy working in a collaborative environment, we encourage you to apply for this position. Join us at MarvyLogic and be a part of building futuristic and impactful solutions that make a difference in various industries. Your experience with emerging technologies and your contributions to our team may help you evolve both professionally and personally, leading to a more fulfilling life.,

As a Silicon Design Validation Engineer at Lattice, you will be part of a dynamic and enthusiastic team working on cutting-edge projects in programmable logic solutions. If you thrive in a fast-paced and results-oriented environment and are passionate about innovation and self-challenge, this role offers you the opportunity to contribute to the validation and performance assessment of building blocks within FPGA. In this role, you will be responsible for validating and characterizing various IPs within the FPGA, such as SERDES, Memory DDR, DPHY, PLL, DSP, Fabric, and I/O components. You will have the chance to work on developing validation and characterization plans, test logic RTL, and drive new silicon product bring-up. Additionally, you will collaborate with design, verification, manufacturing, test, quality, and marketing teams to ensure the successful release of products to production. The ideal candidate for this role will have at least 5 years of experience in Silicon Design Validation, with expertise in High-Speed Serdes Interface characterization, Verilog/VHDL design implementation, and test automation development using languages like Python and Perl. You should also possess strong communication skills, problem-solving abilities, and a proactive mindset. At Lattice, we are focused on collaboration, problem-solving, and innovation. We are a leader in low-power programmable technology, serving customers in various markets such as communications, computing, industrial, automotive, and consumer electronics. By joining Team Lattice, you will be part of a team that is dedicated to creating a smarter, better-connected world through innovative semiconductor products and solutions. If you are motivated to develop a career in Silicon Design Validation Engineering and are looking for a challenging yet rewarding opportunity to work with advanced technologies and equipment, Lattice may be the perfect fit for you. Join us in driving innovation and shaping the future of technology together.,

As an Applications Engineer at Lattice Semiconductor, you will play a crucial role within the Applications engineering organization. This position offers you the opportunity to work alongside a dynamic team where you can actively contribute, learn, and progress in your career. Your primary responsibilities will revolve around leading all aspects of power estimation and correlation for FPGA silicon products, from pre-silicon to post-silicon stages. You will be tasked with managing power-related projects throughout the architecture and production silicon design phases. Collaboration with cross-functional teams to establish power targets, correlation and measurement plans, and achieving system and design level power objectives will be a key part of your role. In this position, you will engage in power estimation, analysis, and correlation activities for individual silicon IPs, sub-systems, and end-user applications. Working closely with the software team, you will ensure accurate modeling of silicon models and measure power and performance goals using the Radiant tool suite. Additionally, you will partner with Sales, Marketing, and Field Applications teams to drive innovation and customer adoption of Lattice products. Your role will also involve assisting in the management of customer escalations and support tickets. To excel in this position, you must possess experience in pre-silicon power prediction and silicon power analysis. Proficiency in circuit or digital design, hardware engineering, silicon design flows, Verilog, and/or VHDL is essential. Hands-on lab experience and familiarity with silicon support, FPGA development, Prime Power or similar tool suites, signal and power integrity analysis, and spice simulations are highly desired skills. Strong English communication skills, both written and verbal, are a necessity. The ability to work independently and collaboratively in a team environment, coupled with excellent analytical and problem-solving abilities, will be crucial for success in this role. You should thrive in a fast-paced environment, effectively prioritize tasks, and manage competing priorities efficiently. At Lattice, we recognize that our employees are our most valuable asset and the driving force behind our success in the competitive global industry. We are committed to offering a comprehensive compensation and benefits program that attracts, retains, motivates, rewards, and celebrates the industry's top talent. Join us at Lattice Semiconductor, an international developer of innovative, low-cost, low-power programmable design solutions. With a global workforce of around 800 individuals who share a common dedication to customer success and a strong determination to excel, we provide an environment where diversity is valued. We welcome applications from all qualified candidates who can contribute to our workplace with their unique perspectives, insights, and values. Experience the energy at Lattice Semiconductor and be part of a team that is passionate about innovation and success.,

At Cadence, we are dedicated to hiring and nurturing leaders and innovators who are eager to leave a mark on the technology industry. With over 30 years of expertise in computational software, Cadence stands as a pivotal figure in electronic design. Our Intelligent System Design approach helps us provide software, hardware, and IP solutions that bring design ideas to life. Our clientele comprises the most groundbreaking companies globally, creating exceptional electronic products across various sectors such as consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial, and healthcare. The Cadence work environment offers a multitude of benefits: - A chance to engage with cutting-edge technology and a culture that fosters creativity, innovation, and impact-making. - Employee-centric policies that prioritize physical and mental well-being, career growth, learning opportunities, and acknowledging achievements based on individual needs. - The "One Cadence One Team" ethos that encourages collaboration within and among teams to ensure customer satisfaction. - A range of learning and development avenues tailored to cater to employees" specific interests and requirements. - Collaborating with a diverse team of enthusiastic, committed, and skilled individuals who consistently go the extra mile for customers, communities, and each other. Job Summary: We seek a professional with over 14 years of experience possessing the following skill set: - Proficiency in RTL design basics utilizing HDLs like VHDL/Verilog/System Verilog. - Comprehensive understanding of AMD (Xilinx) Ultrascale, Versal FPGAs architecture, and experience with Vivado for FPGA place and route. - Competence in defining constraints for FPGAs and conducting Static Timing Analysis. - Familiarity with FPGA prototyping or emulation is advantageous. - Eagerness to learn and explore new technologies, showcasing strong analytical and problem-solving abilities. - Effective written and verbal communication skills, a quick learner, and a team-oriented individual. At Cadence, we are committed to impactful work. Join us in unraveling challenges that others find insurmountable.,

As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. This will involve working on a variety of components including yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to bring cutting-edge products to the market. Collaboration with cross-functional teams is a key aspect of this role to ensure that solutions meet performance requirements. The ideal candidate should have a minimum of 4 to 6 years of work experience in ASIC RTL Design. Experience in Logic design, micro-architecture, and RTL coding is essential. Hands-on experience with the design and integration of complex multi clock domain blocks is a must. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols such as AXI, AHB, APB, clocking/reset/debug architecture are also required. Candidates should have experience in Multi Clock designs and Asynchronous interface. Familiarity with ASIC development tools like Lint, CDC, Design compiler, and Primetime is necessary. An understanding of Automotive System Designs, Functional Safety, Memory controller designs, and microprocessors would be advantageous. The role involves close collaboration with Design verification and validation teams for pre/post Silicon debug. Prior experience in Low power design is preferred. Additionally, expertise in Synthesis and a solid grasp of timing concepts for ASIC are must-haves for this position.,

Qualcomm India Private Limited is seeking a Hardware Engineer with expertise in complex high-performance RTL design, particularly on DSP or processor based sub-systems. You should be proficient in hardware design using Verilog, System Verilog, or VHDL and have knowledge of on-chip bus interface protocols like AXI, APB, and AHB. Experience in model development (SystemC, or C++), RTL to gates synthesis (Synopsys DCG or Cadence Genus), design rule and CDC checking (SVA assertions, Spyglass, 0-in), and working on high-performance low power RTL design is essential. Familiarity with scripting languages such as PERL, Python, TCL, C, etc., is also required. As a Hardware Engineer at Qualcomm, your responsibilities will include developing micro-architecture, designing and documenting specific ASIC modules, and sub-systems. You will own the RTL, ensuring its development, assessment, and refinement to meet power, performance, area, and timing goals. Troubleshooting architecture, design, or verification issues using sound ASIC engineering practices, and leveraging various design tools to enhance design quality will be part of your role. Additionally, you will collaborate with the design verification team to execute the functional verification strategy and contribute innovative ideas for IP core and process flow enhancements. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 2 years of Hardware Engineering experience. Alternatively, a Master's degree with 1+ years of relevant experience or a PhD in a related field will also be considered. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. The company expects all employees to adhere to applicable policies and procedures, including those related to security and protection of confidential information. Please note that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site for submissions. Unsolicited resumes or applications from agencies will not be accepted. For further information about this role, reach out to Qualcomm Careers directly.,

Softnautics is seeking a skilled Verification Engineer to join our VLSI group function. As a Verification Engineer at Softnautics, you will play a crucial role in the architecture development, implementation, and documentation of verification IPs. You will be responsible for various tasks including SV/VUM coding, test-plan development, assertion and functional coverage coding, simulations, and more. Additionally, you will have the opportunity to lead a small team and contribute to the overall success of our projects. Responsibilities: - Understanding the standards and specifications relevant to the project - Developing and documenting architecture details - Hands-on involvement in all aspects of the verification cycle - Ensuring compliance with the latest methodologies - Creating Verification IPs - Defining Functional Coverage matrix and Comprehensive Test plan - Managing regression and achieving functional coverage closure - Integrating and verifying Design Under Test (DUT) for IP delivery sign-off - Leading a small team of engineers Required Skills: - Hands-on experience in complete verification cycle with a strong understanding of verification concepts - Proficiency in Verilog, SystemVerilog, and UVM - Experience in UVM based Verification IP development - Familiarity with AMBA AXI/AHB/APB System buses - Hands-on experience with protocols such as PCIe, Ethernet, USB, DDR, etc. - Knowledge of System Verilog Assertions - Proficiency in scripting for automation, release processes, simulations, and regressions - Excellent written and oral communication skills Desired Skills: - Experience in leading Verification IP development with junior engineers - Exposure to the full verification cycle If you are a confident, self-motivated individual with strong fundamentals in verification engineering, we encourage you to apply for this exciting opportunity at Softnautics. Join our team and be a part of a collaborative environment focused on delivering high-quality results.,

Qualcomm India Private Limited is looking for a Hardware Engineer to join their Engineering Group. As a Qualcomm Hardware Engineer, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams will be essential to meet performance requirements and develop innovative solutions. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3 years of Hardware Engineering experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience will also be considered. You should have 2-6 years of experience in Synthesis, Constraints, and interface timing Challenges, along with a strong domain knowledge in RTL Design, implementation, and Timing analysis. Experience with RTL coding using Verilog/VHDL/System Verilog, micro-architecture & designing cores and ASICs, and familiarity with Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc., will be highly beneficial. Exposure in scripting languages such as Pearl/Python/TCL and strong debugging capabilities are also required for this role. As a Qualcomm Hardware Engineer, you will collaborate closely with cross-functional teams to research, design, and implement performance, constraints, and power management strategies for the product roadmap. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require an accommodation during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. If you are a proactive team player with the ability to independently debug and solve issues, and meet the qualifications mentioned above, we encourage you to apply for this exciting opportunity at Qualcomm India Private Limited.,

As a Staff Engineer - Design Verification at Micron Technology, you will be part of a highly innovative and motivated design team working on cutting-edge memory technologies to develop advanced DRAM and Emerging memory products. Your role will involve verifying high density memory chips with complex circuit capabilities, ultra-high-speed designs, and next-generation DDR/LPDDR technologies. You will collaborate with various design and verification teams globally to ensure the successful completion of design projects. Your responsibilities will include: - Taking ownership of verification and conducting end-to-end analysis of complex block-level custom designs for DDR4, LPDDR4, DDR5, and LPDDR5 memory architectures operating at high speeds. - Guiding and directing the verification effort for all projects undertaken by the team. - Providing verification support by simulating, analyzing, and debugging pre-silicon block level/full chip designs. - Developing test cases and stimulus to enhance functional coverage for DRAM and emerging memory products. - Creating and maintaining test benches and test vectors using simulation tools, running regressions for coverage analysis, and collaborating with international colleagues to develop new verification flows. - Contributing to the development of verification methodologies and environments for advanced DRAM and emerging memory products. - Demonstrating a good understanding of digital/mixed-signal circuits and experience in digital/mixed-signal verification. - Utilizing tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, and Hspice. - Writing Verilog and Real Number Models, as well as building SV testbenches at block and full-chip levels. - Implementing SV and UVM-based verification, with proficiency in scripting using Perl and Python. - Having previous experience in DRAM memory-related fields is advantageous, along with possessing strong communication, debugging skills, and the ability to work effectively in a team. To qualify for this role, you must hold a Bachelor's or Post Graduate Degree in Electronics Engineering or a related field, with 5-15 years of relevant experience. Micron Technology, Inc. is a global leader in memory and storage solutions, driving innovations that enhance the way information is used to enrich life for all. With a focus on customer satisfaction, technology leadership, and operational excellence, Micron offers a range of high-performance DRAM, NAND, and NOR memory and storage products through its Micron and Crucial brands. The advancements made by Micron's team members contribute to the data economy, enabling progress in artificial intelligence and 5G applications across various platforms. For more information, please visit micron.com/careers. If you require assistance during the application process or need accommodations, please contact hrsupport_in@micron.com. Micron Technology strictly prohibits the use of child labor and complies with all relevant laws, regulations, and international labor standards.,

As a Senior Silicon Verification Engineer at AMD, you will play a crucial role in contributing to the advancement of our cutting-edge technologies. You will be part of a dynamic team focused on delivering high-quality solutions to the market, ensuring AMD remains at the forefront of innovation in the industry. Your dedication and expertise will be instrumental in driving the success of our verification engineering efforts and fostering continuous career growth. Your passion for modern processor architecture, digital design, and verification will be key assets in this role. You will collaborate with a diverse team of engineers across different locations and time zones, leveraging your strong analytical and problem-solving skills to tackle complex challenges. Your ability to communicate effectively and work seamlessly with others will be essential in achieving our collective goals. Key responsibilities in this role include developing and maintaining tests for functional verification at the SOC level, building testbench components to support next-generation IP, and enhancing verification libraries for SOC/full-chip level verification. You will also provide technical support to other teams and assist the hardware emulation team in porting RTL to various platforms. Preferred experience for this position includes familiarity with verification methodologies such as OVM, UVM, or VMM, as well as knowledge of Verilog, logic design concepts, and system-level architecture. Proficiency in UNIX environment and scripting languages like Perl or Python, along with strong waveform debug skills using industry-standard design tools, is highly desirable. Experience with UNIX Revision Control tools, bug tracking tools, and verifying multimillion gate chip designs will be advantageous. To be successful in this role, you should hold a BS/MS in EE, CE, or CS, along with 4+ years of design verification experience and 3+ years of OOP coding experience. Demonstrating excellent communication, presentation skills, and the ability to collaborate effectively with cross-functional teams are essential qualities for this position. Familiarity with processors, boot flow, and software development flow would be beneficial in fulfilling the responsibilities of this role effectively. Join us at AMD and be part of a team that is dedicated to pushing the limits of innovation and transforming lives with groundbreaking technologies. Your contributions will be valued, and your career development will be supported as we work together to advance the future of computing experiences.,

You are a highly experienced RTL Design Engineer with 12-20 years of experience, specializing in PCIe IP development. Based in Noida/Bangalore, you will be responsible for designing and supporting the RTL of Cadence's PCIe IP solution. Your role will involve working with existing RTL, adding new features, ensuring customer configurations are clean, supporting customers, and ensuring design compliance with LINT and CDC guidelines. To qualify for this position, you must hold a BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI and have extensive experience as a design and verification engineer, with a focus on RTL design using Verilog. Additionally, you should have experience with System Verilog, UVM-based environments, AXI3/4/5, and preferably PCIe. Previous experience in RTL design of complex protocols and IP development teams is highly advantageous. As a member of the Cadence High-Speed SerDes PHY IP Front end Design team, you will be responsible for defining microarchitecture, leading ASIC design, collaborating with cross-functional teams, mentoring junior members, and fostering a high-performance team culture. Requirements for this role include a Bachelor's degree in Electronics Engineering with at least 7 years of experience, a Master's degree with 5 years, or a Ph.D. with 2 years in Digital Design. You should have hands-on experience in micro-architecting digital blocks, RTL implementation in Verilog/SV, SDC definition, STA, Lint Checks, CDC, and Synthesis. Knowledge of protocols such as Ethernet, USB, PCIe, MIPI(DPHY), and HDMI/Display is desired, along with the ability to work closely with Analog design teams and develop high-speed critical digital circuits and signal processing blocks.,

As an Analog Mixed Signal IC Designer with 4-10 years of experience in Bangalore, you will be responsible for designing, implementing, and verifying analog/mixed-signal IC designs for various motion sensor products. Your role will involve mentoring junior engineers in all areas of product design and evaluating system-level trade-offs for next-generation sensor interfaces. Collaborating with the MEMS design team, you will identify IC architectures to meet performance requirements. Additionally, you will interface with digital design engineers to define and optimize sensor architectures and digital signal processing circuits. Providing guidance to layout engineers on physical design and reviewing layouts for optimal design will be part of your responsibilities. Ensuring timely tape-out of designs adhering to required specifications is crucial. You will evaluate and validate designs in the lab, identify any deviations from requirements, and implement corrective actions. Performing any other duties or tasks assigned from time to time is also expected. The ideal candidate should hold a minimum of a Bachelors/Masters in EE with at least 4 years of industry experience in analog or mixed-signal CMOS circuit design. You should have a thorough understanding of analog and mixed-signal systems, micro-architecture trade-offs, and the ability to develop micro-architectures and high-level Matlab system models. A proven track record in designing low-power, low-noise, precision CMOS analog circuits for high-volume manufacturing is essential. Strong skills in designing various analog/mixed-signal blocks such as MEMS sense amplifiers, Bandgap References, Regulators, Charge pumps, ADCs, Oscillator circuits, and PLLs are required. Experience as an IC lead on at least one project with demonstrated success is preferred. Knowledge of design for test approaches and the development of characterization and production test plans is beneficial. Proficiency in lab and test equipment skills for the debug, characterization, and validation of designs is expected. Being diligent, detail-oriented, and proactive in process and flow improvements are qualities that will contribute to your success in this role. Your responsibilities will also involve developing DACs, Headphone, Line, and Speaker drivers, Proprietary Low-Voltage Line Drivers, DC/DC Converters, and various supporting circuitry in advanced CMOS processes. You will participate in all aspects of the design, from concept to production silicon. Involvement in the specification, architectural development, transistor-level design, SPICE, Matlab, and Verilog modeling and simulation, layout supervision, post-layout simulation, chip-level verification, and lab validation is part of the job. Specifically, you will develop PLL and low-jitter filters and gain hands-on experience with Audio CODEC applications and circuits across different CMOS processes and geometry nodes.,

You should have a minimum of 6-8 years of total work experience with specific expertise in the following areas: - Experience working with USRP N310/X310 (N3xx/X3x0) - In-depth knowledge of FPGA Architecture - Proficiency in writing custom RTL HDL or integrating IP, including VHDL, Verilog, SystemVerilog, Vivado HLS, Xilinx IP, and Vivado Block Diagram - Development experience with RFNoC Blocks - Familiarity with USRP Hardware Driver (UHD) - Ability to write custom FPGA logic in RFNoC Blocks and utilize existing RFNoC Blocks library (e.g., FFT, FIR, Signal Generator, Fosphor) - Understanding of the GNU Radio interface to RFNoC Block - Skills in FPGA debugging and hardware/software integration - Knowledge of appropriate coding styles for FPGAs and trade-offs for density and speed - Thorough understanding of Xilinx ZYNQ 71xx/PL-KINTEX-7-based RFNoC architecture - Capability to comprehend customer requirements, define architecture, and create detailed designs - Strong communication skills to interact effectively with customers - Familiarity with Agile methodology - Bachelor of Engineering or Bachelor of Technology degree (B.E./B.Tech.) This is a full-time, permanent position with a day shift schedule. The role requires individuals with a notice period of up to 30 days. The work location is in person. If you meet the specified qualifications and experience requirements, please apply for this role.,

As a software engineer in the QuestaSim R&D team at Siemens EDA, you will have the opportunity to work on core algorithmic advancements and software design/architecture. Collaborating with a senior group of software engineers, you will play a key role in ensuring the final production level quality of new components and algorithms, as well as in creating new engines and supporting existing code. Your self-motivation, self-discipline, and ability to set personal goals will be essential in contributing to your success in a dynamic environment. Siemens EDA is a global technology leader in Electronic Design Automation software, enabling companies worldwide to develop innovative electronic products efficiently. With a focus on pushing the boundaries of technology in chip, board, and system design, our tools play a crucial role in delivering high-quality products in a complex technological landscape. We are looking for a graduate with a minimum of 2 years of relevant working experience and a degree in CSE/EE/ECE from a reputable engineering college. Proficiency in C/C++, algorithms, data structures, and Compiler Concepts and Optimizations is required. Experience with UNIX and/or LINUX platforms is crucial, along with a solid understanding of Basic Digital Electronics Concepts. Knowledge of Verilog, System Verilog, VHDL, parallel algorithms, job distribution, ML/AI algorithms, and their implementation in data-driven tasks is highly valued. Exposure to Simulation or Formal based verification methodologies would be a plus. The ideal candidate should be self-motivated, capable of working independently, guiding others towards project completion, and possessing strong problem-solving and analytical skills. Join our team at Siemens, where over 377,000 minds collaborate globally to shape the future, one day at a time. We are committed to diversity and equality in our workplace, and we welcome applications from individuals who reflect the communities we serve. If you are curious, creative, and ready to contribute to building tomorrow's innovations, we invite you to join us.,

DIGITAL SIGNAL PROCESSING /DSP : Professional Experience 2+ years Experience in the Design and Development of Radar, communication systems Should have system level architecture design and development experience in wireless communication or Data links or Telemetry or RADAR or RF Seeker Systems/Sub systems. Practical Hands-on experience in VHDL/Verilog languages. Should have good theoretical knowledge and design experience in digital baseband processors. Digital filters, FFT, other signal processing blocks required for communications. Very good skills and abilities to develop and simulate digital signal processing blocks using MATLAB/SIMULINK tools required for Receivers and Transmitters.