R&D Engineering, Sr Engineer

Synopsys

2 - 5 years

20 - 25 Lacs

bengaluru

Posted:2 hours ago| Platform:

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Skills Required

digital synthesis c++ c graph theory electrical engineering rtl engineering vhdl artificial intelligence verilog r fpga computer science fpga design microsoft windows debugging troubleshooting data structures unix programming unix internals

Work Mode

Work from Office

Job Type

Full Time

Job Description

Designing, developing, and maintaining large-scale software systems for FPGA logic synthesis, technology mapping, and timing optimization.

Implementing efficient data structures and algorithms in C/C++ based on functional and technical specifications. Use of AI assistants like Github Copilot.
Collaborating with product validation teams for test planning, execution, and providing customer support.
Troubleshooting, debugging, and resolving issues in both new and existing features of the synthesis toolchain.
Supporting and enhancing existing product features to improve performance and user experience.
Engaging in cross-team discussions to share knowledge and drive continuous product improvement.

The Impact You Will Have:

Advancing industry-leading FPGA prototyping tools, including Synplify Base, Synplify Elite/Apex, ProtoCompiler, and Identify.
Enabling the rapid prototyping and debugging of ASICs through efficient and reliable FPGA synthesis solutions.
Driving the performance, scalability, and cost-effectiveness of FPGA design implementations worldwide.
Supporting customers in achieving faster design cycles and higher product quality through innovative synthesis technologies.
Ensuring Synopsys products remain the gold standard in logic synthesis through technical excellence and continuous improvement.
Fostering collaboration across R&D and validation teams to deliver robust, future-ready solutions.

What You ll Need:

B.Tech or M.Tech in Computer Science, Electrical Engineering, or related field from a reputed institute.
Strong knowledge of data structures, graph algorithms, and C/C++ programming in Windows and/or Unix environments.
Familiarity with digital logic design concepts and RTL (Verilog/VHDL) design flows.
Understanding of timing constraints and static timing analysis.
Working knowledge of FPGA design tools and flows is a plus.
Familiarity with AI programming assistants

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