2434 System Verilog Jobs - Page 28

JD : Verification of Debug Subsystem Requirement: 6 years exp Job Profile & Expertise Requirements: End to end Debug Subsystem verification Expertise in RTL DV, GLS, Coverage closure Understanding of ARM Coresight Debug Architecture Work with architecture and SW teams for debug system requirements, Define VPlan ARM-based CPU debug system understanding - trace, crash debug CPU knowledge and expertise in C Strong SV, UVM knowledge

Work with a dedicated team, verifying analog and mixed-signal building blocks for SOCs, with a focus on the portable, ultra-low power audio markets. Participate in all aspects of the mixed-signal design verification, in partnership with the design engineering team, to develop and implement a mixed-signal verification infrastructure to verify all functional and performance requirements. Required Experience and Skills 5-10 yrs of relevant industry experience Insatiable curiosity to learn about new circuit architectures to advance ultra-low power audio devices A keen understanding of modern mixed-signal verification challenges and solutions. Solid foundation in network theory, amplifier design ...

Role Overview We are expanding our team in India and seeking a Staff Digital Design Engineer to lead the micro-architecture and implementation of advanced digital subsystems for automotive Ethernet communication systems You will collaborate across analog and digital teams to deliver high-performance, reliable solutions for next-generation automotive networks Required Skills + BS/MS/BTech/M Tech in Electrical Engineering or related field + 8+ years of experience in digital design for communication systems + Expertise in Verilog/SystemVerilog, Ethernet or similar protocols, and PHY layer design + Strong understanding of PLLs, clocking schemes, and timing closure + Experience with analog IP int...

In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis . Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirements. Knowledge on Power analysis and PT-PX flow Your Profile You are best equipped for this task if you have: Bachelors or Masters in Electrical/Electronics Engineering with 8+years of relevant experience. Delivery orie...

As a verification engineer with a knowledge of subsystems and SoCs, you will make valuable contributions to a team tasked with verifying the functional correctness of SoC. Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy. Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules. Work with the Emulation/FPGA team in understanding various verification collaterals required for driving stimulus at the board level. Will collaborate with engineers in architecture, design, ve...

1. RTL development and Verification for Digital subsystems, Memory Subsystems including BIST. 2. DFT Insertion and Verification signoff for IO, ARM-PNR, Memory Digital Subsystems with Tessent/Embedded MBIST 3. MBIST, ATPG, RSQ Verification and sign-off. 4. Formal verification, Cross Clock Domain checks, Power/Timing sign off 5. Verify complex Digital subsystems through OVM, UVM methodology, creating the Verification Suit Independently. Skillset: 1. Hands on Experience with RTL, Synthesis, 2. Hands on experience in defining ICC/Synthesis constraints that meets timing closure needs 3. Familiarity with DFT flows includes MBIST, ATPG, RSQ and Verification methodologies and best practices for the...

What You''ll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for ...

We are looking for a skilled SAP CDC Business Analyst (Technical) with 4 to 6 years of experience. The position is based in [location to be specified]. Roles and Responsibility Collaborate with cross-functional teams to analyze business requirements and develop solutions using SAP CDC. Design, implement, and maintain technical documentation for SAP CDC projects. Provide technical support and training to end-users on SAP CDC applications. Develop and maintain reports, dashboards, and other visualizations using SAP CDC tools. Work closely with stakeholders to identify and prioritize project requirements. Ensure compliance with industry standards and best practices in SAP CDC implementation. Jo...

Experience with low-power ASIC design techniques and clock domain crossing Knowledge of AMS verification methodologies Exposure to silicon bring-up and lab validation Familiarity with EDA tools from Synopsys, Cadence, or Mentor Bachelors or Masters degree in Electronics Engineering, Computer Engineering, or related field 8+ years of experience in ASIC digital design, with couple of years of technical leadership role Strong expertise in RTL design, CDC, synthesis, STA, LEC.. Proven experience in mixed-signal ASICs for deep sub-micron and understanding of analog-digital interfaces Familiarity with any scripting languages Excellent problem-solving, communication, and leadership skills Key Respo...

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. Work as part of a world class ASIC design team, building leading edge chips for the Coherent Optics market. Hold a Bachelor or masters degree in electrical or computer engineering Have a minimum 2 ye...

* Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. * Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. * Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. * Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. * Develop verification test plan for both functional and pe...

We are seeking highly motivated individuals with a BS, MS, Btech or Mtech degree in Electronics engineering to be part of the EDA team. Join a great team of engineering professionals who are involved in development, validation & release of IBM CAD tools & methodologies used in designing IBM P & Z microprocessor systems along with system ASICS. In this role, you are expected to enable different flavours of the backend design( RTL-GDS ) flows and assess the quality of tools. Develop automation scripts to aid tool in data analysis/visualization. You are required to have excellent debugging skills and have good understanding of RTL-GDS implementation flow for 5nm and below technologies. We are s...

As a Senior Logic Design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performanc...

Responsibilities: * Collaborate with cross-functional teams on SOC verification * Develop testbenches using System Verilog and Verilog * Ensure compliance with industry standards and customer requirements

People-driven culture This is for an experienced systems engineer (SE) position in the airplane systems engineering organization in the Boeing Commercial Airplanes (BCA) BU. As a member of this team, you will be responsible for System development of aircraft network system, aircraft interface device, computing device, electrical sub-systems, development Assurance (ARP4754A), Validation & Verification and traceability of requirements. Also, you will be responsible for Systems design, system level requirements development, decomposing requirements, testing, and supports FAA certification documents. Position Responsibilities: Demonstrate excellence in development of high-integrity aircraft netw...

Role Overview: You will be responsible for independently executing mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will own tasks related to RTL Design/Module and provide support and guidance to engineers in various areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your role will involve anticipating, diagnosing, and resolving problems while coordinating with cross-functional teams to ensure on-time quality delivery approved by the project manager and client. Additionally, you will be expected to automate design tasks flows, write scri...

As a Senior SOC Verification Lead/Manager at Modern Chip Solutions, you will be responsible for ASIC Verification with a focus on SOC verification. Your key responsibilities will include: - Utilizing System Verilog and Verilog for verification tasks - Implementing UVM methodology for verification purposes - Working with various protocols such as DDR, Ethernet, and PCIe To qualify for this role, you should have: - Minimum 10+ years of experience in ASIC verification - Strong expertise in System Verilog, Verilog, and UVM - Familiarity with protocols like DDR, Ethernet, and PCIe would be advantageous For further details or to express your interest in this position, please contact Anand Arumugam...

As a Verification Engineer at Synopsys, you play a crucial role in ensuring the highest standards of quality in complex system designs. With over a decade of experience in IP verification, you possess a deep understanding of verification methodologies and hardware design intricacies. Your expertise in designing self-checking test benches, developing verification components, implementing functional coverage and assertions using System Verilog, and debugging simulation failures makes you a valuable asset to any team. **Key Responsibilities:** - Designing and implementing self-checking test benches using modern verification techniques. - Developing verification components such as bus functional...

Role Overview: You will be responsible for ASIC RTL design with 10+ years of experience and proficiency in Verilog/System Verilog. Your role will involve working with multiple clock and power domains, integrating and validating various MIPI cores, debugging, and implementing CSI/DSI controllers. Additionally, you will be creating micro-architecture specifications, reviewing vendor IP integration guidelines, running integrity check tools, and participating in design verification and physical implementation processes. Key Responsibilities: - Possess 10+ years of ASIC RTL Design experience and proficiency in Verilog/System Verilog - Work with multiple clock and power domains - Integrate and val...

As an ASIC Intern at NVIDIA, you will be part of our world-class hardware teams, working on cutting-edge designs that power GPUs, CPUs, SoCs, and VLSI systems for next-generation computing platforms. Depending on your interests and skills, you could contribute to architecture, design, or verification across domains such as high-performance graphics, AI processors, VLSI design, and advanced CPU and SoC technologies. **Key Responsibilities:** - C++/System Verilog modelling, test development, and RTL design/debug - Architecture, micro-architecture, and performance verification - Developing verification environments (e.g., UVM), test plans, and reusable components - Scripting and automation with...

As a Lead Product Engineer at Cadence, you will play a crucial role in driving the development of products and technologies, with a significant responsibility for their success. Your expertise in the UCIe domain of Verification IP family, both protocol and product-wise, will be essential in accelerating the adoption of the VIP portfolio at Cadence's top tier customers through pre-sales technical activities. Your main responsibilities will include understanding customer design and verification flows, providing training, developing collaterals, and translating high-level requirements into technical specifications to meet customer needs. Collaboration with R&D, Marketing, and support teams will...

Role : Design Verification Work Location : Preferred Pune WFO, If candidate is found to be excellent Noida or Bangalore Remote options are open Years of Experience : 4+ Years Education Qualification : MS (or higher) in EE/EC/ECC Engineering Skills Must have excellent knowledge of computer architecture and design verification fundamentals. Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies. Experience in developing complex test bench in System Verilog using OVM/ UVM methodology. Hands-on experience in AMBA protocol, PCIe MAC/ USB /MAC/ Bluetooth MAC/ Wifi 802.11 MAC layer protocol. Experience in Low Power Simulation/UPF setup, d...

You will be working as a DV Engineer at Qualcomm India Private Limited with a focus on SOC design verification. Your main responsibility will be to understand the internal requirements and complexities of highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. Your early involvement in DV will also require you to participate in architecture/product definition through early involvement in the product life-cycle. **Key Responsibilities:** - Define verification architecture, develop test plans and build verification environment -...

As a Verification Engineering Manager, you will lead and manage a team of verification engineers, providing guidance, mentorship, and performance feedback. You will ensure the definition and implementation of test and verification plans, collaborating with design, architecture, and other cross-functional teams to ensure alignment on project goals and requirements. Monitoring and analyzing coverage reports will be crucial to ensure thorough verification, and you will be responsible for identifying and resolving verification issues and bugs to ensure timely project delivery. Continuously improving verification processes, methodologies, and tools will also be a key part of your role. Managing p...

As a Synthesis & STA engineer, you will be responsible for performing RTL Synthesis to optimize the Performance/Power/Area of the designs. Your role will involve DFT insertions such as MBIST and SCAN, setting up Timing Constraints for functional and Test Modes, and Validation. You will be expected to create Power Intent for the designs, verify power intent on RTL, run static Low-Power checks on gate level netlists, and ensure Logic Equivalency Checks between RTL to Gates and Gates to Gates. Collaborating with the Design/DFT/PD teams, you will set up signoff Static Timing Analysis and ECO flows to achieve timing closure. Additionally, you will be involved in Power Analysis, estimating power a...