Qualcomm SOC DV Engineer

You will be working as a DV Engineer at Qualcomm India Private Limited with a focus on SOC design verification. Your main responsibility will be to understand the internal requirements and complexities of highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. Your early involvement in DV will also require you to participate in architecture/product definition through early involvement in the product life-cycle. **Key Responsibilities:** - Define verification architecture, develop test plans and build verification environment - Work with design team to understand design intent and bring up verification plans and schedules - Verify Subsystems and Full SoC using advanced verification methodologies - Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard - Develop test plan to verify all low power aspects across all modes of verification RTL, PA-RTL, PA-GLS and Formal - Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals - Assist in silicon bring-up, debug and bring-up activities **Qualifications Required:** - B.E/B.Tech/M.E/M.Tech in Electronics with 5+ year experience in verification domain - Strong fundamentals in digital ASIC verification - Experience in IP/SS/SoC level verification of medium to high complexity design - Familiarity with system level HW and SW Debug techniques and Verification requirements - A good understanding of the complete verification life cycle (test plan, testbench through coverage closure) - Strong System Verilog/UVM based verification skills & Experience with Assertion & coverage-based verification methodology - Experience w/ PSS or higher-level test construction languages is an added advantage - Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI - Good understanding of low power design techniques - Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells - Experience with UPF/CPF based power-aware verification - Working knowledge of GLS, PAGLS and scripting languages such as Perl, Python is a plus - Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc - Knowledge of one or more of Multimedia design blocks such as Display/Camera/Video/GFx - Knowledge of one or more of peripheral blocks verification such as PCIe/USB/UFS/I3C Please note that Qualcomm India Private Limited is an equal opportunity employer and is committed to providing reasonable accommodations to support individuals with disabilities during the application/hiring process. You may contact Qualcomm's toll-free number or email disability-accommodations@qualcomm.com for assistance.,