Senior/Principal ASIC RTL Design Engineer

As a Senior/Principal ASIC RTL Design Engineer at our company based in Bangalore, Karnataka, you will have the opportunity to take ownership of the end-to-end RTL design process for complex SoC or large subsystem blocks. Your responsibilities will include defining micro-architecture from specs, writing high-quality synthesizable SystemVerilog/Verilog RTL, and ensuring successful tapeout and silicon bring-up. Responsibilities: - Define micro-architecture and write synthesizable RTL for SoC-level or large subsystems. - Own design bring-up, integration, and ensure timing, power, and area targets are met. - Lead design reviews, bug resolution, and support silicon validation and post-silicon debug. - Collaborate with DV team to define test plans, assertions, and coverage goals. Qualifications Required: - 8+ years of hands-on ASIC RTL development experience with multiple production ASIC tapeouts. - Strong skills in SystemVerilog/Verilog RTL, micro-architecture, clock/reset design, low-power techniques, and standard bus protocols. - Experience collaborating with physical design on synthesis constraints, timing closure, and ECOs. - Proven silicon bring-up experience for owned blocks/subsystems. Nice to have: - Exposure to coherency protocols, cache/memory controllers, DDR/PCIe subsystems, and security/crypto blocks. - Knowledge of SVA for design-level assertions, performance modeling, and power/perf analysis. - Scripting skills for design productivity using Tcl/Python. If you are an engineer who enjoys real ownership and wants your design decisions to make a significant impact, this role is worth exploring. We look forward to welcoming you to our team.,