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Description
Lead Physical Design Engineer | Hyderabad, India | Experience : 8+ Years Domain : Semiconductor – Physical Design About the Role: We are looking for a Lead Physical Design Engineer with deep expertise in working on mature/legacy nodes such as 180nm, 130nm, 110nm, 90nm, 65nm, 45nm, 40nm . This role involves end-to-end ownership of physical design flow, from floorplanning to GDSII, with a strong emphasis on timing closure, IR/EM analysis, and physical verification . The ideal candidate should be technically hands-on and able to lead block-level or chip-level efforts with minimal supervision. Key Responsibilities: End-to-end execution of RTL to GDSII physical design for block- or full-chip Perform floorplanning, placement, clock tree synthesis (CTS), routing, and signoff Manage timing closure , IR drop, EM, and congestion challenges effectively Handle physical verification (LVS, DRC, ERC, antenna checks) using standard sign-off tools Work closely with RTL, STA, DFT, and package integration teams Mentor junior team members and support physical design reviews and planning Required Skills: Proven experience on older technology nodes (e.g., 180nm, 130nm, 110nm, 90nm, 65nm, 45nm, 40nm ) Hands-on with tools like Cadence Innovus, Synopsys ICC2, PrimeTime, Calibre, StarRC Expertise in timing constraints, physical ECOs , and sign-off methodologies Strong understanding of low power design, DFM, and hierarchical flows Ability to lead technically and communicate effectively across teams Educational Qualification: B.E./B.Tech or M.E./M.Tech in Electronics, VLSI Design, or related disciplines Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com Show more Show less
