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Qualcomm
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Senior Lead/Staff RTL Design Engineer

Senior Lead/Staff RTL Design Engineer

Qualcomm

6 - 11 years

18 - 22 Lacs

Noida

Posted:1 month ago| Platform:

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Skills Required

soc design synthesis asic development timing analysis verilog physical design usb soc amba apb rtl design axi fpga asynchronous rtl coding ahb protocols sta asic primetime hardware engineering rtl dft timing closure rf pcie logic design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Job Area: Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Principal Duties and Responsibilities:

5+ Years of Experience in Logic design /micro-architecture / RTL coding

Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs.

Experience in Verilog/System-Verilog is a must.

knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.

Work closely with the SoC DFT, Physical Design and STA teams

Hands on experience in Low power SoC design is required

Hands on experience in Multi Clock designs, Asynchronous interface is a must.

Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required.

Understanding of constraint development and timing closure is a plus.

Experience in Synthesis / Understanding of timing concepts

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Senior Lead/Staff RTL Design Engineer