Senior Design Verification Engineer - CPU & SoC Verification

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Job Summary :

Required Skills & Experience

• Proven expertise in SystemVerilog, UVM, and coverage-driven verification.
• Strong experience in CPU/core-level verification (RISC-V, ARM, or custom processor).
• Good understanding of CPU microarchitecture concepts pipeline, branch prediction, MMU, cache
  

• Hands-on experience in SoC-level verification, including interconnect (AXI/AHB/APB), memory subsystem, and IP integration.
• Proficiency with EDA tools (Synopsys VCS, Cadence Xcelium, or Mentor Questa).
• Strong debug skills using waveform viewers (DVE, Verdi, SimVision).
• Scripting skills in Python, Perl, or Shell for regression and automation.
• Familiarity with emulation, FPGA validation, or formal verification is a plus.
  

Key Responsibilities

• Develop and own CPU core and SoC-level verification environments using SystemVerilog and UVM.
• Define and drive test plans, coverage goals, and verification methodologies for CPU pipelines, memory hierarchy, cache coherence, and interconnects.
• Verify integration of CPU subsystems, interconnect fabrics, memory controllers, and peripherals in the SoC.
• Develop scoreboards, monitors, checkers, and assertions for functional verification.
• Perform constrained-random, directed, and coverage-driven testing to achieve full verification closure.
• Debug simulation failures, analyze waveforms, and work closely with RTL designers to resolve design issues.
• Interface with architecture, design, firmware, and emulation teams to ensure complete functional validation.
• Drive functional coverage closure and maintain metrics for verification completeness.
• Contribute to automation and regression management, including scripting in Python/Perl/Tcl.
• Mentor and guide junior engineers, review their test plans and verification environments.