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Senior Analog Layout Engineer-High Speed Analog Chip TSMC 5nm

8 years

0 Lacs

india

Posted:1 day ago| Platform: Linkedin logo

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Skills Required

layout support development technology signal integration planning circuit simulation design drc lvs reliability optimization correlation debugging cadence communication

Work Mode

Remote

Job Type

Full Time

Job Description

Job Title: Senior Analog Layout Engineer High-Speed Analog Chip (TSMC 5nm)

Experience: 8+ YearsLocation: Remote / India (must support USA/Canada time zone)Travel: Willing to travel to the U.S. for project release (as required)

Role Overview

We are looking for a Senior Analog Layout Engineer to work on a high-speed analog chip development in advanced TSMC 5nm technology. The candidate will operate as an individual contributor, responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision.This role demands deep technical expertise in chip-level integration, bump planning, and ESD implementation, along with a good understanding of circuit simulation concepts. The engineer will work closely with SoC, Circuit, and Digital teams to ensure robust layout quality and performance.

Key Responsibilities

  • Own end-to-end schematic-to-layout design for high-speed analog and mixed-signal circuits.
  • Perform floor planning, bump and pad-ring design, and ESD implementation at the chip level.
  • Collaborate with SoC, circuit, and digital design teams for layout integration and signoff.
  • Ensure layouts meet all DRC, LVS, ERC, EM/IR and reliability standards.
  • Handle layout matching, shielding, and parasitic optimization for high-speed performance.
  • Support simulation correlation and assist in debugging layout-related circuit issues.
  • Work independently, taking full ownership of assigned IPs and layout deliverables.
The ideal candidate should have a strong understanding of chip-level layout planning, bump design, ESD implementation, and parasitic optimization, along with a basic understanding of circuit simulation. You'll work closely with SoC, circuit, and digital design teams, contributing as an individual contributor in a fast-paced, global environment.

Skills Required

Hands-on experience with TSMC 5nm, Cadence Virtuoso, Calibre/PVSStrong background in high-speed analog IPsExpertise in floorplanning, ESD, bump planning, shielding, and matchingExcellent communication and ability to coordinate with global teams

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