RTL Design -Senior Lead(Turing-AI/ML)

General Summary:

Today, more intelligence is moving to edge devices, and mobile is becoming the pervasive AI platform. Building on the smartphone foundation, Qualcomm envisions making AI ubiquitous - expanding beyond mobile and powering machines, vehicles, and Internet of things. Be part of the group that is working on technology which will bring cognition to all connected devices. Join the machine learning team responsible for ASIC IP design and integration of leading-edge technologies in the area of image post processing, machine learning, and IoT.We are searching for a lead ASIC Design Engineer to be part of the

AI Processor Design Team responsible for developing hardware to support AI/ML and video processing systems.

Preferred Qualifications

• Masters- Electrical Engineering , Computer Engineering,
• Exposure to functional safety, Automotive(ASIL) ASIC design.
• Experience with cache control and/or video processing function design/verification
• Detail oriented with strong analytical and debugging skills
• Strong communication (written and verbal), collaboration, and specification skills
• Ability to work well in a team and collaborate with your colleagues worldwide

Minimum Qualifications

• Previous experience working on complex high-performance RTL design, preferably on DSP or processor based sub-system.
• Expert in hardware (RTL) design in Verilog, System Verilog or VHDL.
• Knowledge of standard on chip bus interface protocols (AXI, APB, AHB)
• Experience with some of below.
  • Model development (SystemC, or C++)
  • RTL to gates synthesis (Synopsys DCG or Cadence Genus)
  • Design rule and CDC checking (SVA assertions, Spyglass, 0-in)
  • Work on high performance low power RTL design.
  • Scripting languages (PERL, Python, TCL, C, etc.)

PRINCIPAL DUTIES AND RESPONSIBILITIES:

• Develop micro-architecture, design and program specific documentation
• Design and modelling of compute ASIC modules and sub-systems.
• RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.
• Resolves architecture, design, or verification problems by applying sound ASIC engineering practices
• Use of various design tools (Synopsys, Compiler Linting, CDC, LEC, CLP etc.) to check and improve design quality
• Help the design verification team execute on the functional verification strategy.
• Generates innovative ideas for IP core and process flow improvements

Level of Responsibility:

• Working independently with little supervision.
• Making decisions that are moderate in impact;
• Using deductive and inductive problem solving; multiple approaches may be taken/necessary to solve the problem; often information is missing or incomplete; intermediate data analysis/interpretation skills may be required.
• May be solicited during strategic planning period.

Minimum Qualifications: