Principal Engineer

Western Digital

8 - 12 years

10 - 14 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

cadence ncsim electronics c++ sbt usb simvision simulation ece soc design verification vhdl rtl design fpga analyzer perl system verilog protocols communication skills python interfaces c ip engineering uvm verilog spectrum eda tools waveform

Work Mode

Work from Office

Job Type

Full Time

Job Description

BE/ME in ECE, Electronics, or equivalent
8-12 years of experience in RTL design verification for Block/IP/Sub-system/SOC
Knowledge in synthesis and timing analysis
Experience with FPGA verification - Advantage
Experience & Knowledge with verilog and System Verilog for Verification , SVA, UVM - Strong Advantage
Deep knowledge of the following tools is an advantage: cadence NCSim, simvision, vmanager, any simulator, and waveform debug EDA tools from mentor, Synopsys
Knowledge simulation environment System Verilog - UVM based advantage
Developing testbench for constraint random environment, Metric driven verification
Root-cause design issue and able explain in text form clearly with design knowledge.
Experience in standard protocols such eMMC, UFS, USB, PCIe, and DDR4 advantage
Knowledge with Perl/python advantage
Problem-solving: Ability to break the problem into small parts and apply relevant techniques to drive required outcomes
Good communication and/or interaction skills among groups - local and abroad
Ability to communicate multiple interfaces inside the company
innovation : able to use technology in new ways to create more efficient organization and improve alignment between technology initiatives and business goals.
Familiar with version control systems such as GitQualifications
BE/ME in ECE, Electronics, or equivalent

8-13 years of experience in RTL design verification for Block/IP/Sub-system/SOC

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