7 Cadence Ncsim Jobs

Company Description At Sandisk, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible. At our core, Sandisk is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we've been doing just that. Our technology helped people put a man on the moon. We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world's biggest companies and public cloud, Wester...

Your Role As a SoC GLS Verification Engineer , you will play a key role in verifying complex SoC designs through Gate-Level Simulation (GLS). You will work closely with design and verification teams to ensure functional correctness, timing accuracy, and overall quality of silicon-ready designs. Your expertise in GLS methodologies and debugging will be critical in delivering high-performance, reliable SoCs. In this role, you will: Perform GLS using Zero Delay , SDF , and Post-Layout GLS (PAGLS) techniques. Debug and resolve issues in gate-level simulations to ensure timing and functional correctness. Develop and maintain SystemVerilog/UVM testbenches for GLS environments. Collaborate with cro...

BE/ME in ECE, Electronics, or equivalent 8-12 years of experience in RTL design verification for Block/IP/Sub-system/SOC Knowledge in synthesis and timing analysis Experience with FPGA verification - Advantage Experience & Knowledge with verilog and System Verilog for Verification , SVA, UVM - Strong Advantage Deep knowledge of the following tools is an advantage: cadence NCSim, simvision, vmanager, any simulator, and waveform debug EDA tools from mentor, Synopsys Knowledge simulation environment System Verilog - UVM based advantage Developing testbench for constraint random environment, Metric driven verification Root-cause design issue and able explain in text form clearly with design know...

Your Role As a SoC GLS Verification Engineer , you will play a key role in verifying complex SoC designs through Gate-Level Simulation (GLS). You will work closely with design and verification teams to ensure functional correctness, timing accuracy, and overall quality of silicon-ready designs. Your expertise in GLS methodologies and debugging will be critical in delivering high-performance, reliable SoCs. In this role, you will: Perform GLS using Zero Delay , SDF , and Post-Layout GLS (PAGLS) techniques. Debug and resolve issues in gate-level simulations to ensure timing and functional correctness. Develop and maintain SystemVerilog/UVM testbenches for GLS environments. Collaborate with cro...

About The Role Your Role As a SoC GLS Verification Engineer , you will play a key role in verifying complex SoC designs through Gate-Level Simulation (GLS). You will work closely with design and verification teams to ensure functional correctness, timing accuracy, and overall quality of silicon-ready designs. Your expertise in GLS methodologies and debugging will be critical in delivering high-performance, reliable SoCs. In this role, you will: Perform GLS using Zero Delay , SDF , and Post-Layout GLS (PAGLS) techniques. Debug and resolve issues in gate-level simulations to ensure timing and functional correctness. Develop and maintain SystemVerilog/UVM testbenches for GLS environments. Colla...

Job Description Total experience (5 -7 years) with SOC GLS experience of minimum 3+ years Hands on experience in GLS (Zero Delay, SDF, PAGLS) Excellent debugging skills and fixing issues Knowledge in SV/UVM and test bench flow Good experience in EDA tools such as Synopsys Verdi, Cadence NC Sim. Understanding of SOC Architecture Education Qualification: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.

As a DFT Verification Engineer, your role involves developing and executing pre-silicon verification test plans for DFT features of the chip. This includes verifying DFT design blocks and subsystems using complex SV or C++ verification environments. You will also be responsible for building test bench components, composing tests, assertions, checkers, and validation vectors to ensure verification completeness. Additionally, debugging regression test failures and addressing areas of concern to meet design quality objectives are key responsibilities. Key Responsibilities: - Develop and execute pre-silicon verification test plans for DFT features of the chip - Verify DFT design blocks and subsy...