122 Power Management Jobs - Page 4

Qualifications Educational qualification: Bachelor s or Master s degree in Computer Science or Electronics or Electrical Engineering or related field. Experience : 3-6 years Skills : Work Experience: Atleast 3+ years of relevant Industry or Academic experience with Linux Kernel Skills/experience: Excellent knowledge of OS fundamentals, Data structures, Linux kernel and its device driver model Excellent programming skills and expert level knowledge of C Excellent debugging skills, using kernel tracers as well as JTAG and GDB debuggers Good knowledge of memory management, interrupt handling and power management in Linux Good understanding of ARM v8/v9 CPU and cache architectures Proficient in Git for development and patch/branch management Experience with python, perl, rust, shell scripting is a plus Know how of Linux Kernel upstream patch submission process with patches merged in kernel.org as well as experience working with community development boards (Dragonboards/Pandaboards) is a double plus Independent and self-motivated problem solver and strategic thinker Effective written and verbal communication Excellent interpersonal and teamwork skills

Post Silicon Validation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Experience in silicon lab validation for power management ICs. Experience with validation of Mixed-signal ICs. Experience in validation test planning, test development, execution, debug and report preparation. Hands-on experience of using lab equipment such as oscilloscope, signal analyzer, signal generator, etc. familiarity of programming and scripting languages like Python, Perl Experience in automation using NI Labview is an advantage Understanding of power management ICs, architecture, specifications interpretation is required Debug skills to zero in on an issue, coordination with cross-functional teams is required Skills Experience LabVIEW, PMIC, Post Silicon Validation, System Validation, Testing Validation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Pre-Silicon Validation Engineer Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Creating test environments, checker strategies, and test generators for validating embedded power management firmware in the SOC Communicating effectively, coordinating and working with firmware developers and SOC integration teams Potentially participating in the debug of failures in silicon and developing new testing strategies to detect these failures on pre-silicon models Mentoring junior members of the team in their development You should have 3-5 years of experience in the following areas: SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM Reading and interpreting technical specs and Register Transfer Level (RTL) code SW development skills (Unit Testing, Test Driven Development) Hands-on Debug Preferred Skills and Experience: Expertise in any of one domain like Audio, Performance, power management will be a huge plus 4+ years’ experience with writing validation plans and implement those validation plans Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

- Lead the architecture, design and development of Power Management for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Server SoC power management features. * Experience with hardware to model correlation * At least 1 generation of silicon bring up experience * In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) * Proficiency of RTL design with Verilog or VHDL * Knowledge of at least one object oriented or functional programming language and scripting language. Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Introduction As a Hardware Engineer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in todays market. Your role and responsibilities Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification : Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Position:Embedded C,Linux kernel, Power Management. Experience:8-12 years Location:Bangalore Education:B.E in Electronics & Communication Engineering. TessolveSemiconductors a venture of Hero Electronix, part of $5B Hero Group companies a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Currently we are 2300+ employees worldwide. We are Global Multi- National Company having Engineering and Sales presences in India, Malaysia, Singapore, USA, UK, Europe, and China. Tessolve has strategic and sustainable growth plan to ensure the business stability to our valued customers and to protect the career of our employees even under disturbed Business situations. Technical Skillset Required: KEY RESPONSIBILITIES: Contribute to the development and optimization of power management features in the Linux kernel, focusing on heterogeneous core architectures. Develop, test, and refine kernel patches related to power management, scheduler enhancements, and S0ix state optimization. Debug and resolve core idle state issues within the Linux kernel to improve system efficiency and performance. Work on DisplayPort (DP) and Alternate Mode (Alt Mode) functionalities in the kernel, ensuring seamless integration and performance. Collaborate with cross-functional teams to design and implement new features and improvements in the Linux kernel. Participate in code reviews, provide feedback, and ensure adherence to best practices and coding standards. Stay updated with the latest developments in the Linux kernel community and contribute to upstream projects. Document design specifications, technical details, and user guides for developed features and patches.

NES SOC Architecture team is looking for an outstanding engineer to work on definition of NEX SoC(s) for Intel Server, Client and IoT platforms. In this role, you will develop and drives end-to-end SoC architecture for highly optimized, modular, and scalable SoC, based on hardware features, requirements, and interoperability of hardware and software throughout the product life cycle.You will collaborate across disciplines to analyze workloads, identify opportunities for improvement, determine priorities, and balance trade-offs. Responsibilities include: Determining functional requirements based on product goals, use cases, and workload analysis. Defining SoC architecture to meet product requirement and deliver architecture specifications. Evaluates feasibility trade-offs and explores and defines new approaches and novel architectures for SoC. Invents, conceptualizes, and specifies microarchitecture and architectural features for next-generation products to deliver optimized SoC for multiple segments from high performance computing to extreme low-power products. A successful candidate will demonstrate. Broad knowledge of SoC architecture. Performance, power trade-off understanding. Deep expertise in domains such as reset, clock, coherency, debug, power management, performance evaluation Exceptional communication skills. Collaborates with design engineers, system engineers, verification engineers, structural design engineersto improve the overall design of SoC and overcome constraints. Work will include a combination of individual contribution and leveraging team participation through mentoring and leadership of technical initiatives. Qualifications: Minimum Qualifications: Bachelor's degree or higher in Computer Science or Electronics Engineering, 15+ years relevant experience in Silicon development in Arch/Uarch, Modeling, Designincluding multiple project development life cycles with at least one as lead architect or lead u-architect.

Min 20 years of experience in Power Distribution Sector. Relevant experience in power utilities & electricity distribution projects. Should have done at least one project of Rs. 1000 Cr or above in the capacity of Team Leader or similar.Developing project plan and implementing the same. Documenting daily, weekly, monthly and yearly report and submitting the same to the top management. Encouraging and assisting the team members and workforce for effective work resulting in improvement.

About the Role : We are seeking highly motivated and skilled Power Management Firmware Engineers to join our team and contribute to the development of cutting-edge power management solutions. In this role, you will be responsible for designing, developing, and maintaining firmware for power management subsystems, ensuring optimal power efficiency and system performance. Key Responsibilities : Design, develop, and maintain firmware for power management subsystems, including : a. BIOS power management features (e.g., ACPI, sleep/hibernate states, power profiles) b. Platform power management (e.g., CPU/device power states, hot-plug, dynamic voltage and frequency scaling) c. PCIe power management and link states d. Analyze and debug power-related issues. e. Optimize power consumption across the system. - Collaborate with hardware and software engineers to ensure seamless system integration. - Stay abreast of the latest power management technologies and industry standards. - Contribute to the development and documentation of firmware specifications. Required Skills : Mandatory : - Very strong in C language programming and debugging - Working knowledge of git/gerrit Key Skillsets : - Good understanding and experience with BIOS, power management and PCIe - Good knowledge SoC power management - CPU/Device power states, hot-plug etc - Strong knowledge of UEFI BIOS, ACPI. - AGESA knowledge is a big plus - Experience with embedded systems development and debugging. - Strong analytical and problem-solving skills. - Excellent communication and collaboration skills. Desired Skills (Optional) : - Experience with assembly language programming. - Knowledge of scripting languages (e.g., Python, Perl). - Experience with Agile development methodologies. - Experience with power measurement and analysis tools. Keywords Power Management,BIOS,PCI-e,SoC,Embedded System,Perl,C,git,Firmware*

Job Details: Job Description: Develops and drives Power Modelling and Estimation framework for highly optimized, modular, and scalable SoCs. Actively works on power analysis, power optimization, simulation and roll-ups. Should be hands on PTPX/Power artist and other industry standard power estimation tools. Collaborate with the Various SoC and IP teams on various power projections and requirements, including silicon power capture and correlation with pre-si estimates. Perform data mining analysis at the RTL and gate-level to define relevant micro-architectural transactions for high-level power estimation Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. What we need to see Minimum Qualifications: Bachelors degree in Electrical Engineering, Computer Engineering or similar with 10+ years of relevant work experience, e.g. in consumer electronics or semiconductor companies. 5+ years' experience with system design of small, medium, and large power management or power modelling systems including hands on experience with PTPX/Power artist tools. Preferred Qualifications: Bachelors degree in Electrical Engineering, Computer Engineering or similar with 12+years of relevant work experience Strong ability to manage multiple projects, grow knowledge and capabilities of the power team, and perform hands-on testing Background in analog or digital power design. Job Type: Experienced Hire Shift: Shift 1 (India)

Min 20 years of experience in Power Distribution Sector. Relevant experience in power utilities & electricity distribution projects. Should have done at least one project of Rs. 1000 Cr or above in the capacity of Team Leader or similar.Developing project plan and implementing the same. Documenting daily, weekly, monthly and yearly report and submitting the same to the top management. Encouraging and assisting the team members and workforce for effective work resulting in improvement. Keywords Team Management,Site Management,Power management,Electricity Distribution*,Site Incharge,Electrical Project*,Power Distribution*,Electrical,Power Engineering,Power Utility*,Utility & Electricity*

Introduction As a Hardware Engineer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in todays market. Your role and responsibilities Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 1-3 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification : Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

2 Y+ Experience in Energy Automation & electrical distribution. Passionate about Sustainability, Energy Efficiency and new Energy landscape topics. Expertise in Industrial automation software, PLC programming & SCADA - Knowledge of Schneider PLCs and tools is preferred. Expertise in Industrial communication protocols including Modbus TCP/IP Programming in Structured text and or Ladder logic in compliance with IEC61131. Programming in IEC61499 Automation Expert - (Preferred) Knowledge of Electrical systems and Power Management Systems (Controls, Power inverters, BESS, PV inverters, Gensets, etc.).

Requirement: 2Y+ Experience in Energy Automation & electrical distribution. Passionate about Sustainability, Energy Efficiency and new Energy landscape topics. Expertise in Industrial automation software, PLC programming & SCADA - Knowledge of Schneider PLCs and tools is preferred. Expertise in Industrial communication protocols including Modbus TCP/IP Programming in Structured text and or Ladder logic in compliance with IEC61131. Programming in IEC61499 Automation Expert - (Preferred) Knowledge of Electrical systems and Power Management Systems (Controls, Power inverters, BESS, PV inverters, Gensets, etc.)

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

locationsIndia, Bangalore time typeFull time posted onPosted 5 Days Ago job requisition idJR0274956 Job Details: About The Role : Foundry Services (FS) is an independent foundry business that is established to meet our customers' unique product needs. With the first Open System Foundry model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient, and sustainable source of supply. This job opportunity in FS will be part of the Customer Solutions Engineering (CSE) group which is responsible for the portions of the system foundry that brings the best of Intel technologies to FS customers, differentiating and accelerating their solutions from architecture to post-silicon validation. We are looking experienced Floorplan Engineer to work on Foor plan, die estimation, Power planning of high performance designs . Responsibilities include Establishes the integration plans for die with optimization for package and board constraints. Bump planning, Die file generation , closing loop with package team on signal and power bump placement restrictions Create physical database for the IP or SoC. Collaborate with architects to optimize the placement of IPs for latency as well as die area/aspect-ratio. Collaborate with the design teams on clocking and dataflow to deliver the physical block level floorplans for APR. Derive specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies. Coordinate with power delivery team on trade-offs for metal allocation for signal and power. Have excellent understanding on, die-per-reticle/good-die-per-wafer maximization, and right technology selection on metal layers usage maximization Good knowledge on RDL routing and efficient usage higher metal layers Performs integration of all dies in a package and completes the relevant checks before tape-out. Qualifications: Qualification : 12+ Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field. Must have led multiple SOCs in capacity of SOC Floorplan lead. Strong Expertise in Design planning, die estimation, Good understanding on package and board level requirement . Must have knowledge on clocking , high speed design signal routing, industry standard protocols and IP architecture; Good understanding on relevant areas of Library / Memory / technology/submicron issues . Teamwork / flexibility / ability to thrive in a dynamic environment are very important Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Intel Foundry is dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. As stewards of Moore's Law, we innovate and foster collaboration within an extensive partner ecosystem to advance technologies and enable our customers to design leadership products. Our strategic investments in geographically diverse manufacturing capacities bolster the resilience of the semiconductor supply chain. Leveraging our technological prowess, expansive manufacturing scale, and a more sustainable supply chain, Intel Foundry empowers the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of the Foundry Services business unit within Intel Foundry, a customer-oriented service organization that is dedicated to the success of its customers with full P&L responsibilities. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 30+ Days Ago job requisition idJR0270512 Job Details: About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 5+ years of industry experience, or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 3+ years of industry experience Years of experience must include at least three of the following skills: Hardware architectures, system level IC design implementation knowledge of how to create end use scenarios IP level or SoC level validation experience Processor-based SoC level verification, in native Verilog, SystemVerilog and UVM mixed environments Verification tools such as VCS, waveform analyzer and/or third-party VIP/BFM integration (e.g. Synopsys VIPs) UVM verification Strong understanding of design concepts and ASIC flow Preferred Qualifications and experience that will make you stand out: Prior work on GDDR memory, power management, peripherals, datapath verification or PCIe Protocol is desirable Understanding of AXI-AMBA. Protocol variants is desirable Strong technical background in FPGA prototype emulation and debug Proven technical background in silicon validation, failure analysis and debug Validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART Prior hands-on automation script development and optimization using C/C++, Python Good understanding of embedded firmware/software development process Functional knowledge and experience in JTAG Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Qualcomm is building on its core strengths in wireless and compute technologies and is in the middle of the biggest technology revolution in the Automotive space. While Qualcomm has pioneered connected car technologies for over a decade, it is now playing a critical role in the evolution of Automotive Infotainment, Telematics, ADAS/Autonomous Driving & its supporting technologies. We are investing in several bleeding edge technologies such 5G, Cellular V2X, Computer Vision, AI/Deep Learning etc., and are working closely with global Automakers/Tier-1s, standards bodies, consortiums and operators on pushing the boundaries. Qualcomm Automotive Team is looking for dynamic individuals who can make difference on many technology forefronts in Automotive space, join our growing multisite engineering organization. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience. 3+ years of work experience with Programming Language such as C, C++, Java, Python, etc. Bachelors or Masters in Engineering At-least 9 to 16 years experience in below areas. Hands on experience of driver development on any RTOS Handson Experience in Autosar software development Detailed understanding SoC hardware blocks - Clocks, PLLs, GPIO, Interrupt Controllers (GIC), Peripherals (SPI/I2C/PCIE/CAN/Ethernet/USB/UFS), power management Experience in Linux kernel architecture, device drivers and memory management. Embedded multimedia product development experience in Android Smartphones, Network based Graphics/Video/Camera/Display/Computer Vision products Experience in ISO26262/functional safety Exposure to one or more of below technology areas is a plus:- Multiprocessor Architecture, ARM processors, caching, interrupts, etc., Virtualization technologies across CPU and MM hardware accelerators

General Summary: Qualcomm is seeking experienced Design Verification (DV) engineers to verify high-performance and low-power CPUs, focusing on power management features including boot, reset, clock gating, power gating, voltage/frequency management, limit management, and throttling. Roles and Responsibilities: Develop and execute comprehensive power management verification plans, collaborating closely with CPU design and verification teams. Use simulation and formal verification methodologies, including writing checkers, assertions, and stimulus generation. Verify power intent with methodologies such as UPF (Unified Power Format). Work with system architects, software, and SoC teams to validate system-level use cases. Collaborate with emulation teams to enable verification on emulators and FPGA platforms. Debug and triage failures occurring in simulation, emulation, or silicon testing. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years experience, OR Master's degree with 3+ years experience, OR PhD with 2+ years experience in Hardware Engineering. Strong experience in power management verification (clock gating, power gating, UPF, DVFS/DCVS, throttling). Skilled in embedded firmware programming with assembly and C language. Proficient in C/C++, scripting languages, Verilog/SystemVerilog. Solid understanding of power management features in CPUs and CPU-based SoCs. Preferred Qualifications: Good understanding of CPU architectures and microarchitectures. Deep knowledge of digital logic design, microprocessor debug features, DFT architecture, and microarchitecture. Experience with advanced verification techniques such as formal verification and assertions. Familiarity with DFT and structural debug methodologies including JTAG, IEEE1500, MBIST, scan dump, and memory dump.

General Summary: Qualcomm is at the forefront of the automotive technology revolution, leveraging its expertise in wireless and compute technologies to drive innovation in Automotive Infotainment, Telematics, ADAS/Autonomous Driving, and related domains. The Automotive Compute Platform team seeks a seasoned Senior Technical Lead to guide multi-site engineering teams in delivering cutting-edge automotive software and hardware solutions. This leadership role will focus on optimizing embedded compute platforms, driving compliance with ASPICE and ASIL standards, and collaborating closely with global automakers, Tier-1 suppliers, and standards bodies. Key Responsibilities: Lead and mentor multiple teams of architects, technical leads, and engineers specializing in compute hardware and software optimization for automotive platforms. Define and execute strategic roadmaps aligned with Qualcomm's vision for best-in-class automotive service capabilities. Drive robust processes for requirement specification, prioritization, solution development, and system validation methodologies within a global engineering context. Manage stakeholder alignment across product roadmaps, delivery schedules, and feature capabilities. Oversee release management processes ensuring quality and compliance. Engage hands-on with embedded software development, including low-level drivers, firmware, kernel and user-space components on multi-core ARM/CPU, GPU, DSP, and specialized accelerators. Lead design and development efforts for heterogeneous embedded SoC platforms, utilizing JTAG/ICE debugging tools. Spearhead compliance efforts for automotive functional safety standards including ISO26262. Facilitate cross-geography collaboration with partners, customers, and senior management. Drive business process improvements and digitization initiatives in automotive software engineering. Minimum Qualifications: Bachelor's degree or higher in Engineering, Computer Science, Information Systems, or related field. 13+ years of experience in embedded software design, development, and support for multi-core ARM/CPU platforms. Strong programming skills in C and C++. Hands-on experience with embedded platforms including low-level driver and firmware development, real-time OS (RTOS), and kernel architecture. Experience leading medium to large technical teams. Proficient in driver development for RTOS environments and Autosar software stacks. In-depth understanding of SoC hardware blocks (clocks, PLLs, GPIO, interrupt controllers, peripherals such as SPI/I2C/PCIe/CAN/Ethernet/USB/UFS, and power management). Experience with Linux kernel architecture, device drivers, and memory management. Proficient in debugging and development using JTAG or In-Circuit Emulators (ICE). Preferred Qualifications: Demonstrated leadership experience working with senior management and distributed global teams. Excellent verbal and written communication skills. Experience in ISO26262/functional safety compliance. Exposure to multiprocessor architectures, virtualization technologies, caching, and interrupt handling. Experience driving process transformations and digital service enablement. Self-motivated, hands-on leader who actively engages in technical details to steer team success. Additional Skills: Familiarity with programming languages such as Java and Python. Ability to work across geographies and cultures effectively.

Job Area Engineering Group > Hardware Engineering General Summary Qualcomm is looking for strong Design Verification (DV) engineers in Bangalore to verify power management features in high-performance, low-power CPUs. Roles and Responsibilities Verify power management features including Boot, Reset, clock gating, power gating, voltage/frequency management (DVFS/DCVS), limit management, and throttling Develop comprehensive test plans in collaboration with CPU design and verification teams Use simulation and formal verification methods to execute test plans; write checkers, assertions, and develop stimulus Verify power intent using Unified Power Format (UPF) methodologies Collaborate with system architects, software, and SoC teams to validate system-level use cases Work with emulation teams to run verification on emulators and FPGA platforms Debug and triage failures in simulation, emulation, and silicon environments Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years hardware engineering experience OR Master's degree with 3+ years experience OR PhD with 2+ years experience Additional Requirements: 3+ years experience with power management verification in CPU or SoC environments Proficiency in assembly, C, C++ programming and scripting languages Experience with Verilog/SystemVerilog Strong understanding of CPU architectures and power management features such as clock gating, power gating, UPF, DVFS/DCVS, throttling Experience in embedded firmware implementation Preferred Qualifications Deep knowledge of CPU microarchitecture, digital logic design, debug features, and DFT (Design for Testability) architecture Experience with advanced verification techniques including formal verification and assertions Knowledge of DFT methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump

Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Infra Systems Architect for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. This position will be responsible for Technical and hands on role mainly for high level architecture and micro-architecture development. Design the prototype or experiments for proof of concept for initial power, area or latency benefits Candidate ready to learn new protocol and sub-systems to support different segments of infra solutions Work with design team to resolve queries and ensure the completeness of design Participate in development of the testplan and test scenarios for bug free RTL Preferred Qualifications 8+ years of experience in IP architecture, micro-architecture and design. Good understanding of SOC. Possesses expertise in any one of the following technical areas is a plus:DDR, Interconnects, SOC power management, clock/reset, UBWC, Encryption, ECC Understanding of ARM architecture (Coherency, bus interconnects, Security, arch evolution) Good communication and work with minimal supervision Collaborate with Perf, Design and System team stakeholders in developing solutions Experience with Verilog, logic design principles with timing, area and power implications. Experience in testplan development, UVM, will be a great asset Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHI. Good Understanding of concurrency, bandwidth, latency and system level aspects Education Requirements:Bachelor's degree in Electrical Engineering required, Master's or Doctorate preferred

General Summary Qualcomm is a global leader in wireless and compute technologies, now accelerating innovation in the Automotive space . The Automotive Compute Platform Team is seeking a Senior Technical Lead to drive the evolution of Automotive Infotainment, Telematics, ADAS/Autonomous Driving, and other cutting-edge technologies like 5G, Cellular V2X, Computer Vision, and AI/Deep Learning. Key Responsibilities Lead multiple teams of architects, technical leads, and engineers across compute hardware and software in optimization efforts. Drive compliance with ASPICE and ASIL functional safety standards. Define strategic roadmaps aligned with Qualcomm's vision for automotive services. Manage requirements specification, prioritization, and solution development with global stakeholders. Define automotive use cases and system validation methodologies. Oversee robust release management processes. Hands-on involvement in technical issues and active leadership to drive team success. Minimum Qualifications Education: Bachelor's in Computer Engineering, Computer Science, Electrical Engineering, or related field with 8+ years of software engineering experience OR Master's degree with 7+ years experience OR PhD with 6+ years experience Experience: 20+ years in embedded systems software design, development, and support on multi-core ARM/CPU platforms. Strong C/C++ programming skills. Experience with embedded platforms, including low-level drivers, firmware, kernel, and user-space components. Software development for heterogeneous SoC platforms with ARMs, GPUs, DSPs, and hardware accelerators. Proficiency in JTAG or ICE debugging tools. Real-time embedded software development experience. Hands-on leadership of medium to large technical teams. Experience with driver development on RTOS. Autosar software development experience. Detailed understanding of SoC hardware blocks (Clocks, PLLs, GPIO, Interrupt Controllers, Peripherals such as SPI, I2C, PCIE, CAN, Ethernet, USB, UFS). Linux kernel architecture, device drivers, and memory management. Preferred Qualifications Self-motivated with excellent verbal and written communication skills. Proven experience collaborating with cross-geography engineers, partners, and customers. Experience engaging with senior management in corporate settings. Expertise in business process transformation and digitized service enablement. Willingness to dig into technical details and lead hands-on. Knowledge of ISO 26262 / functional safety highly preferred. Exposure to multiprocessor architecture, ARM processors, virtualization technologies. Programming Languages Experience C, C++, Java, Python (4+ years)

Position: ASIC RTL Design Lead (SI90FT RM 3217) Job Description: Innovate, implement, and verify RTL code for complex PHY sub systems dealing with high speed blocks using Verilog/System Verilog knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must. Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution Previous experience with storage systems, protocols, in NAND flash /DRAM controller PHY Basic understanding of PHY system level concepts Experience in PHY architecture, power management and Registers understanding to interact with FW design. Proficient in C, C++, Lint Excellent interpersonal skills and Team Player High level of integrity and commitment to quality and timeliness. Understanding of Hardware Block Diagrams, Schematics Understanding of PHY Architecture document and programming guidelines Understanding of PHY integration guidelines implementation Strong can-do attitude Job Category: Embedded HW_SW Job Type: Full Time Job Location: Bangalore Experience: 9+ YEARS Notice period: 0-30 days