SOC Power Design - Sr. Staff

General Summary:

• Work with cross-functional teams on SoC Power and architecture for mobile SoC ASICs.

Skills/Experience

• At least 8-15 years of experience are required in the following areas:
• Low power intent concepts and languages (UPF or CPF)
• Power estimation and reduction tools (PowerArtist/PTPX,Calypto)
• Power dissipation and power savings techniques- Dynamic clock and voltage scaling
• Power analysis (Leakage and dynamic) and thermal impacts
• Power Software features for power optimization
• Voltage regulators including Buck and Low Drop out
• ASIC Power grids and PCB Power Distribution Networks

Additional skills in the following areas are a plus:

• Mobile Baseband application processors chipset and power grid understanding
• UPF-based synthesis and implementation using Design Compiler
• Structural low power verification tools like CLP or MVRC
• Outstanding written and verbal communication skills

• Responsibilities
  • Defining chip and macro level power domains
  • System Level Power Modeling
  • Mixed signal power analysis
  • Power Island/Power Gating/Power Isolation
  • Structural Low power design of level shifter and isolation cell topology and associated rules
  • Architectural analysis and development of digital power optimization logic/circuits/SW
  • Work with Power Management IC developers for power grid planning
  • Creating detailed architecture and implementation documents

  Education Requirements

  • Required: Bachelor's, Computer Engineering and/or Electrical Engineering
  • Preferred: Master's, Computer Engineering and/or Electrical Engineering

Minimum Qualifications:

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