401 Physical Verification Jobs - Page 11

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. Qualification/Requirements 6 to 9 years experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc, Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc) Understanding layout effects on the circuit such as speed, capacitance, power and area etc Ability to understand design constraints and implement high-quality layouts Ability to understand design hierarchy and different architectures for Memory designs. Excellent problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Excellent verbal and written communication skills.

As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the physical integration and verification team , you will work closely with the physical design implementation, IP teams and fab contacts to achieve quality tapeout and first pass silicon success. THE PERSON: A successful candidate will work on block level and SoC physical integration, verification and tapeout with physical design engineers. The candidate is expected to be detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work with PD team on subsystem and block level physical verification and signoff Work closely with physical design implementation and signoff team to achieve faster TAT Work closely with CAD team to come up with new flows and methodologies in the physical verification domain PREFERRED SKILLSET: 3+ years of relevant experience Sound knowledge of physical verification and design flows Hands on experience on industry standard tools such as Calibre and ICV Sound understanding for DRC/LVS decks. Should be able to make updates as required. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

1. Financial / Strategic Strategize and plan to create a robust secondary logistics function with an aim to drive overall effectiveness and efficiency, thereby positively impacting TLC (Total Logistics Cost) Engage and sustain relationships with high performing transporters for continuous and reliable and sustainable services thereby facilitating an edge over other competitors Prepare yearly budget for logistics department and share the same with the Logistics Head for approval Ensure adherence to the approved budget Take initiatives to drive growth for DCBL and ensure sustained growth in line with long-term and short-term objectives of the organization 2. Monitoring and Control Monitor and control all activities involving transportation, stock control and the flow of goods Monitor the secondary performance with respect to targets set by the Sales team, and take appropriate measures to prevent/correct fluctuations in target achievement Ensure timely uploading of freight on SAP and approve fluctuations as per analysis 3. Logistic Operations Ensure timely delivery of goods to the dealers / distributor shops thereby driving achievement of sales targets for DCBL Manage the transporter activities and ensure regular follow ups with them for timely transportation of material to customers Review the performance of transporters and share feedback with management for decision making. ensure association with high performing vendors for cost and service related benefits Implement new techniques and processes to drive overall cost effectiveness and efficiency of the function Utilize Logistics analysis being conducted by the Logistics analytics (role) and ensure decisions are made basis the insights. Drive reduction in Total Logistics cost, while maintaining high service levels. Ensure time and cost optimized rake planning to effectively reduce logistics cost Appoint C&Fs after carefully checking backgrounds, their associated network and also compare proposals Manage all operational matters pertaining to CNFs, their disputes, change of rates, union issues, etc. and address all queries / issues for smooth functioning of Secondary Logistics Function Ensure physical verification of stocks at warehouses by the regional team by dedicated surprise / special visits/ audits Ensure complete safety of logistics, including all systems, processes and personnel involved Ensure efficient and effective vendor management/agreement including driving key capability building initiatives for key vendors Ensure initiation and sensitization of the employees towards digitization and automation of the processes Focus on utilization of advanced business analytics tools to derive key insights critical for the success of the organization 4. Self/ Team Development Review and monitor performance of team members and provide requisite developmental support/ inputs Recommend training as required for team s development Develop the team and update their knowledge base to cater the organization need Strategize avenues for enhancing employee satisfaction in the function, resulting in high engagement levels of employees

1. Financial / Strategic Strategize and plan to create a robust secondary logistics function with an aim to drive overall effectiveness and efficiency, thereby positively impacting TLC (Total Logistics Cost) Engage and sustain relationships with high performing transporters for continuous and reliable and sustainable services thereby facilitating an edge over other competitors Prepare yearly budget for logistics department and share the same with the Logistics Head for approval Ensure adherence to the approved budget Take initiatives to drive growth for DCBL and ensure sustained growth in line with long-term and short-term objectives of the organization 2. Monitoring and Control Monitor and control all activities involving transportation, stock control and the flow of goods Monitor the secondary performance with respect to targets set by the Sales team, and take appropriate measures to prevent/correct fluctuations in target achievement Ensure timely uploading of freight on SAP and approve fluctuations as per analysis 3. Logistic Operations Ensure timely delivery of goods to the dealers / distributor shops thereby driving achievement of sales targets for DCBL Manage the transporter activities and ensure regular follow ups with them for timely transportation of material to customers Review the performance of transporters and share feedback with management for decision making. ensure association with high performing vendors for cost and service related benefits Implement new techniques and processes to drive overall cost effectiveness and efficiency of the function Utilize Logistics analysis being conducted by the Logistics analytics (role) and ensure decisions are made basis the insights. Drive reduction in Total Logistics cost, while maintaining high service levels. Ensure time and cost optimized rake planning to effectively reduce logistics cost Appoint C&Fs after carefully checking backgrounds, their associated network and also compare proposals Manage all operational matters pertaining to CNFs, their disputes, change of rates, union issues, etc. and address all queries / issues for smooth functioning of Secondary Logistics Function Ensure physical verification of stocks at warehouses by the regional team by dedicated surprise / special visits/ audits Ensure complete safety of logistics, including all systems, processes and personnel involved Ensure efficient and effective vendor management/agreement including driving key capability building initiatives for key vendors Ensure initiation and sensitization of the employees towards digitization and automation of the processes Focus on utilization of advanced business analytics tools to derive key insights critical for the success of the organization 4. Self/ Team Development Review and monitor performance of team members and provide requisite developmental support/ inputs Recommend training as required for team s development Develop the team and update their knowledge base to cater the organization need Strategize avenues for enhancing employee satisfaction in the function, resulting in high engagement levels of employees

Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tape out. Experience: 7-15Y Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2. Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs. Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. Capable of developing sign-off methodologies/flows and providing support to larger teams. Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset. Experience in floor planning is a plus Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 3-10 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

Stock maintaining of Raw materials, consumables items, engineering items, electrical items and other related parts • Scheduling and maintaining delivery cycles of raw materials, engineering items and consumables items • Maintaining stocks on daily basis - Excel and Tally • Checking of invoices and bills received from suppliers, take signs from responsible authorities, scanning of invoices and bills and handover the same documents to office for further process • Maintaining sufficient stocks for RM,consumables, electric and engineering items • Keep tracks of courier items and handover of courier to courier services and collecting parcels on regular basis. • Planning of required raw materials with the of Plant Head and other items required for production with the help of Purchase manager. • Dealing and monitoring sales of scrap materials with scrap vendors • Assist in Procurement of electrical and engineering items required for maintenance dept as per requirements • Purchasing emergency and needed items from local stores

Technical Skill Set - SOC level Floor Plan, PNR, IO Ring Design, Timing Closure, Physical Verification, Power planning and analysis, ECOs on 7nm and 10nm technology nodes. Must-Have Hands-on experience on Full chip floor plan, Full chip PNR, and Design Partitioning. Hands-on experience in IO Planning, Bump Plan and RDL Routing. Experience in ECOs, Synthesis and STA, and Power analysis. Hands-on experience in Physical verification. Hands-on experience on 7nm and 10nm technology nodes. Good-to-Have Effective communication skills to interact with cross-functional teams.

1. Financial / Strategic Strategize and plan to create a robust secondary logistics function with an aim to drive overall effectiveness and efficiency, thereby positively impacting TLC (Total Logistics Cost) Engage and sustain relationships with high performing transporters for continuous and reliable and sustainable services thereby facilitating an edge over other competitors Prepare yearly budget for logistics department and share the same with the Logistics Head for approval Ensure adherence to the approved budget Take initiatives to drive growth for DCBL and ensure sustained growth in line with long-term and short-term objectives of the organization 2. Monitoring and Control Monitor and control all activities involving transportation, stock control and the flow of goods Monitor the secondary performance with respect to targets set by the Sales team, and take appropriate measures to prevent/correct fluctuations in target achievement Ensure timely uploading of freight on SAP and approve fluctuations as per analysis 3. Logistic Operations Ensure timely delivery of goods to the dealers / distributor shops thereby driving achievement of sales targets for DCBL Manage the transporter activities and ensure regular follow ups with them for timely transportation of material to customers Review the performance of transporters and share feedback with management for decision making. ensure association with high performing vendors for cost and service related benefits Implement new techniques and processes to drive overall cost effectiveness and efficiency of the function Utilize Logistics analysis being conducted by the Logistics analytics (role) and ensure decisions are made basis the insights. Drive reduction in Total Logistics cost, while maintaining high service levels. Ensure time and cost optimized rake planning to effectively reduce logistics cost Appoint C&Fs after carefully checking backgrounds, their associated network and also compare proposals Manage all operational matters pertaining to CNFs, their disputes, change of rates, union issues, etc. and address all queries / issues for smooth functioning of Secondary Logistics Function Ensure physical verification of stocks at warehouses by the regional team by dedicated surprise / special visits/ audits Ensure complete safety of logistics, including all systems, processes and personnel involved Ensure efficient and effective vendor management/agreement including driving key capability building initiatives for key vendors Ensure initiation and sensitization of the employees towards digitization and automation of the processes Focus on utilization of advanced business analytics tools to derive key insights critical for the success of the organization 4. Self/ Team Development Review and monitor performance of team members and provide requisite developmental support/ inputs Recommend training as required for teams development Develop the team and update their knowledge base to cater the organization need Strategize avenues for enhancing employee satisfaction in the function, resulting in high engagement levels of employees

Technologies from 28nm, 20nm, 14nm, 10nm, 7 nm. Block level floorplanning, power planning and IR drop analysis. Timing closure Multimode multi corner optimization and closure. Clock tree synthesis and advanced clock tree implementation. Block level timing closure with sign off STA . Block level ECO implementation involving netlist level logical changes. Library performance analysis and fine tuning for implementation. Excellent debugging skills in implementation issues and ability to come up with creative solutions.

: We are looking for a highly skilled & experienced PD expert to join our Flows & Methodologies team. The candidate must be experienced, hands-on and have robust understanding of physical design including Floorplan, Power-plan, Place & Route, UPF, CTS. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope of Responsibilities: As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Physical Design methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC Place & Route, UPF, Formal Verification, Floorplan & Power-Plan You will work with EDA Vendors to proactively review latest tools and flows offerings in Physical Implementation domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. Work with EDA Vendors to review and resolve blocking issues You will be an actor of change for deploying new tools & methodologies across the organization Qualifications Specific skills & knowledge : Bachelor or Master or Ph. D. in Electronics Engineering and specialization in VLSI domain 10+ years of hands-on experience in Physical Design : UPF, Formal & Physical verification, floorplan, power-plan, Place & Route Proven experience in delivering physical implementation closure methodology ensuring timing & physical convergence Experience in Synopys & Cadence tool sets (Fusion Compiler, Innovus) , low geometry node issues, working with EDA team in reviewing & resolving blocking issues in project Experience in customizing flows & methodology to meet low power & area objectives of SoC Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can - do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team

Audit and report about the stock in our factory. Present to the management any missing stock information Attention to detail and ability to work independently Passionate about auditing and able to work on selected sundays when required for audit

Job Title: Jr. Engineer - Stores Job Purpose: Control Panel Manufacturing Business Role Type: Individual Contributor Preferred Professional Education: Diploma/Degree Electrical/Electronic Engineering. Job Summary: Materials receipt, physical verification, GRN posting in SAP, Materials Issue to Production in FIFO, Proper storage & preservation of materials. Perpetual Inventory, monthly & quarterly physical inventory. 5S systems, Kaizen, Maintain safety of 3M & quality standard. Roles & Responsibilities: Incoming materials documents verification, receipt & acknowledge, if any transit damaged report the same immediately to concern dept. Ensure physical verification as per Invoice/packing list, if any discrepancy found, inform to the buyer with proper supporting documents. GRN posting in SAP & storage right materials in right location as per WMS systems. Ensure material stored in defined bin location as per WMS systems. Period physical inventory & perpetual inventory of store material. Maintain 5S & take initiative for Kaizen implementation, good housekeeping of materials storage area. Operation wise advance Kit preparation for electrical/electronic materials. Materials issued to production against operation wise reservation. Follow safety rules & regularization strictly at Plant. Co-ordinate with team for shift wise timely materials feeding to assembly line. Work experience: 2 to 5 years of experience in inventory control management in electrical/electronic manufacturing company. Skills Required: Managing Complexity Taking Ownership Living Customer Orientation Enabling Collaboration Promoting personal growth Driving change Sound Knowlagent of electrical & electronic component. Knowledge of SAP Hana S4 /R3 MM module. Must be very detailed oriented and strive to achieve high quality results. Ability to multitask, prioritize, organize and adhere to written procedures. Professionalism, a positive attitude and willingness to work as a team. Must be able to simultaneously handle the demands of internal and external customers

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times Initiate & drive cost out measures Explore new suppliers & expedite development Maintain business relationship with all supplier for best outcome Travelling /Visit to suppliers required. (As per business requirement) Excellent Communication skills (Written/Oral)

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

Maintain accurate records of all incoming/outgoing material Ensure proper stacking/storage of material Conduct physical stock verification & reconcile with records Issue materials as per approved indents Record material movement in ERP or registers Required Candidate profile Coordinat with purchase & accounts departments for material receipts & invoicing Monitor & control inventory to prevent over or understocking Assist in audits by providing complete documentation

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Job Responsibilities Implementing RTL to GDS2 flow Floor-planning, Placement, CTS, Routing using physical design tools Synthesis, LEC Debugging timing constraints , Static timing analysis as part of Physical Design flow Extraction, Physical Verification(LVS/DRC) Crosstalk analysis, EM/IR analysis Position requirements BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute 2-6 years of relevant experience Hands on experience doing physical design and timing closure of complex blocks Strong understanding of timing, power and area trade-offs and optimization of PPA Knowledge of clock tree synthesis optimization to meet latency, skew goals Understanding timing Constraints and debugging through PD flow Knowledge of Design Margins timing corners, Timing analysis and signoff timing closure Good Debugging skills in resolving Congestion and Timing, SI/CrossTalk Analysis and Write Timing/Functional ECOs Exposure in signoff Power, IR and Physical Verification at both block and chip level is desirable Experience with scripting and automation - Perl/Tcl/shell and implementation flows Good verbal and written communication skills to work effectively with teams spread geographically

THE ROLE: Join AMD as we push the boundaries of whats possible in graphics and compute technology. We are seeking a talented RTL Physical Design Engineer to contribute to the development and optimization of our cutting-edge CDNA and RDNA graphics IP. This role involves transforming sophisticated RTL designs into robust and efficient physical layouts, critical to the performance of our next-generation graphics and compute solutions. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities: Physical Design Implementation: Translate complex CDNA and RDNA graphics IP RTL designs into optimized physical layouts. Utilize industry-leading EDA tools for synthesis, place-and-route (PnR), and physical verification processes to take the design thru mock-taepout Performance Optimization: Focus on power, performance, and area (PPA) optimization to meet the stringent requirements of high-performance graphics and compute products. Collaborate with architecture and front-end design teams to align RTL design with physical constraints and objectives. Verification and Timing Closure: Conduct static timing analysis (STA) to ensure robust timing closure and sign-off for graphics IP. Implement and verify design rule checks (DRC), layout versus schematic checks (LVS), and power grid analysis tailored to CDNA and RDNA requirements. Collaboration and Communication: Work closely with cross-functional teams, including architects, RTL designers, and verification engineers to ensure seamless integration and functionality of graphics IP cores. Provide feedback and suggest improvements to design methodologies and processes to push the technology envelope further. Documentation and Reporting: Maintain comprehensive design documentation, methodologies, and updates. Prepare detailed reports on design progress, performance metrics, and any technical challenges encountered. PREFERRED EXPERIENCE: Domain Expertise: Experience with working on complex design and optimizing for performance, power, and area. Technical Proficiency: Proven track record in RTL synthesis, place-and-route (PnR), and static timing analysis (STA) for complex IP cores. Proficiency with industry-leading EDA tools, such as Synopsys Design Compiler, Cadence Innovus, and timing analysis tools like PrimeTime. Experience with low-power design methodologies and techniques for high-performance graphics IP. Design and Verification: Successful completion of full-chip sign-off, including design rule checks (DRC) and layout versus schematic (LVS) checks. Strong skills in signal integrity analysis, including crosstalk and IR drop evaluations. Process Technology: Experience working with advanced semiconductor process nodes (e.g., 7nm, 5nm, or below). Knowledge of process-related challenges and optimization techniques for graphics applications. Scripting and Automation: Proficiency in scripting languages such as Perl, Python, or TCL to automate design flows and improve efficiency. Experience developing and maintaining scripts for design rule checks and optimization processes. Problem-Solving and Innovation: Demonstrated ability to solve complex design challenges using innovative approaches. A track record of contributing to the improvement of design techniques and methodologies in a graphics-focused engineering team. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the physical integration and verification team , you will work closely with the physical design implementation, IP teams and fab contacts to achieve quality tapeout and first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC physical integration, verification and tapeout with physical design engineers. The candidate is expected to be detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Drive Full chip physical integration and verification (DRC/LVS, ERC, DFM checks) Work with fab and fab contacts for all the tapeout activities leading to final tapeout. Work closely with physical design implementation and signoff team to achieve faster TAT Work closely with CAD team to come up with new flows and methodologies in the physical verification domain PREFERRED SKILLSET: Experience : More that 12 years of relevant experience. Driven multiple tapeouts across different technology nodes Sound knowledge of full chip physical integration and verification flows Hands on experience on industry standard tools such as Calibre and ICV Sound understanding for DRC/LVS decks. Should be able to make updates as required. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Should be skilled in INNOVUS,Fusion compiler and Calibre must have worked on latest Tech nodes , with very good hand on experience with PV flows like DRC.ERC,Perc,antenna ,ESD checks , should have atleast basic knowledge on handling tcl scripting

Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. Experience in PnR tools like ICC/Innovus with regards to physical convergence must. Good understanding of PD flows and overall backend tool flow would be beneficial. Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and DRV. TCL/PERL Scripting is plus. Hands on experience :Innovus/Fusion Compiler , Tech lef is preferable. Interested candidates can share their resumes to shubhanshi@incise.in

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is necessary. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc. Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience and collaborating with cross functional teams will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Multiple foundries experience is an added plus. Minimum Educational Qualification : Educational Bachelor's, Electrical or Electronics Engineering or equivalent Role And Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, EM, quality check and documentation. Responsible for on-time delivery of block-level/top-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Should have good experience in working with cross-functional team. Ensure standard processes and procedures are followed to resolve all client queries. Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations to timely deliverable with high quality. Troubleshoot all client queries in a user-friendly, courteous, and professional manner. Offer alternative solutions to clients (where appropriate) with the objective of retaining customers' and clients' business. Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client. Contribute to effective project-management. Effectively communicating with engineering teams in different Geographical locations to assure the success of the layout project. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders.

Lead a team of Zonal Incharge- CPO in the cluster for Customer service delivery & assurance. Liaison with builders for PROW - cost effective & faster building level permissions Providing inputs related to potential new partners from the zone Identification of upcoming buildings in the zone Upkeep of existing relationship with building management and update the Building tenancy details as per the defined format. Vendor management of Network partners (CPO, Vistaar, 3rd Party OHF & NNI, TCL, BSO) L2 survey Access for 3rd Party Vendors for OHF cable/UBR at TTL POP with Field Operations approval MRN processing & capitalisation in S4HANA basis WBSE, physical verification in AMS of TTL assets deployed at customer location- MUX, CPE, Routers, UBR, EPABX etc.. Ensure execution at customer site RFS & end to end testing for all on-net and offnet media - OSP/IBD, ODN, UBR, Copper using different CPEs - MUX, MMC, L2 switch, copper modem, GPON etc. Responsible for customer delivery and testing from handoff point outside TTL PoP to customer location Scheduling engineer for testing Coordination with NOC for testing & troubleshooting on need basis Performance management of existing partners Maintenance Activity at Customer location - Infra, IBD, ISP, CPE along with AMS updates TP to Own media, Copper to FTTH migration Ensuring timely asset retrieval with ATN in S4HANA & AMS update Field testing for TRAI as per regulation requirements OSP/IBD services allocation and SRF wise data maintaining with all associated inputs. The aspirant for Zonal Incharge Lead - CPO role must have in-depth understanding about the customer requirements & to manage the same with the partners. The role will handle issues related to customer management for service delivery & assurance. Span of control: 4 to 6 Staff Key Customer Customer Program Management, Customer Service Management, NW Planning, NW Ops & Finance Necessary Preferred Skills In depth Knowledge of ROW/PROW. Adheres to the industry standards. Assumes full responsibility for the safety and security of the team. Determines the scope, budget, and schedules for customer service delivery existing and new projects. Submits weekly project status reports to the reporting managers. Delivers within the stipulated time. Follows engineering standards and work as per market engineering specifications. Maintains records of all projects Inspects deployments of customer deliveries as per the quality standards Working experience with prominent telecom operators for Estate management, Service Delivery & Assurance Qualification PGDM/B.E./B.Tech (Telecom / Communication / Instrumental) Overall Work Experience 12 to 15 Years in service delivery & assurance Behavioural Attributes Positive thinking Willingness to work in a competitive environment. Team player Good listener