401 Physical Verification Jobs - Page 10

Role & responsibilities:- Conduct Periodical audit and take corrective actions for deviation as per company guidelines for internal controls. Ensure compliance of Standard Operating Process by the store finance team. Inventory controlling in terms of review of shrinkage Prepare and review the MIS for stores and ensure completeness of the same. Accounting & Reconciliation of revenue, cost, receivables & payables. Do trouble shooting for store finance related customer issues. Physical verification of Fixed assets. Compliance of Indirect taxes. Liasioning with the bankers and finance company and various authorities and consultants to resolve any store related issues. Scheduling and training of store finance team Compilation of various reports required by SO from time to time

Role & responsibilities:- Conduct Periodical audit and take corrective actions for deviation as per company guidelines for internal controls. Ensure compliance of Standard Operating Process by the store finance team. Inventory controlling in terms of review of shrinkage Prepare and review the MIS for stores and ensure completeness of the same. Accounting & Reconciliation of revenue, cost, receivables & payables. Do trouble shooting for store finance related customer issues. Physical verification of Fixed assets. Compliance of Indirect taxes. Liasioning with the bankers and finance company and various authorities and consultants to resolve any store related issues. Scheduling and training of store finance team Compilation of various reports required by SO from time to time

Role & responsibilities:- Conduct Periodical audit and take corrective actions for deviation as per company guidelines for internal controls. Ensure compliance of Standard Operating Process by the store finance team. Inventory controlling in terms of review of shrinkage Prepare and review the MIS for stores and ensure completeness of the same. Accounting & Reconciliation of revenue, cost, receivables & payables. Do trouble shooting for store finance related customer issues. Physical verification of Fixed assets. Compliance of Indirect taxes. Liasioning with the bankers and finance company and various authorities and consultants to resolve any store related issues. Scheduling and training of store finance team Compilation of various reports required by SO from time to time

The ASIC Back-End Head is responsible for leading the physical design and implementation of Application-Specific Integrated Circuits (ASICs), ensuring optimal performance, power efficiency, and manufacturability. Key Responsibilities Strategic LeadershipDefine and execute the ASIC back-end design roadmap. RTL to GDSII Flow ManagementOversee synthesis, floorplanning, placement, routing, timing closure, and sign-off. Physical Design OptimizationEnsure Power, Performance, and Area (PPA) targets are met. EDA Tool ExpertiseWork with Synopsys, Cadence, Mentor Graphics tools for ASIC implementation. Cross-functional CollaborationCoordinate with design, verification, DFT, and packaging teams. Tape-Out & Manufacturing SupportEnsure smooth transition from design to fabrication. Key Skills & Qualifications Extensive experience (15yrs+) in ASIC physical design and implementation. Expertise in timing analysis, power optimization, and physical verification. Strong leadership, communication, and problem-solving skills. Bachelor's/Master's degree in Electronics, Electrical, or related Engineering discipline. Reinvent your world.We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Senior Staff Physical Verification Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development. Play Video Job Description Category Engineering Hire Type Employee Job ID 11903 Remote Eligible No Date Posted 22/06/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and proactive professional with a strong technical background in physical design and physical verification at the IP, block, and full-chip levels. You excel in addressing challenges associated with advanced FinFET and GAA processes and have a proven ability to deliver high-quality results in complex design environments. Your expertise spans RTL-to-GDS implementation, physical verification, and signoff methodologies, and you are adept at collaborating with cross-functional teams to achieve optimal design solutions. You are detail-oriented, innovative, and thrive in a collaborative environment where continuous improvement is valued. Your strong communication skills enable you to effectively engage with internal teams and external customers, ensuring alignment and success in project execution. With a passion for technology and a commitment to excellence, you are eager to contribute to the development of cutting-edge semiconductor solutions that shape the future. What You ll Be Doing: Conceptualizing, designing, and productizing state-of-the-art RTL-to-GDS implementations for SLM monitors using ASIC design flows. Designing on-chip Process, Voltage, Temperature, Glitch, and Droop monitors to track silicon biometrics. Performing physical verification tasks, including DRC, LVS, PERC, ERC, ESD, EM, and antenna cleaning. Collaborating with the Place & Route team to resolve full-chip/IP/block-level layout integration issues and drive physical verification closure. Coordinating with internal IP owners to address IP-related issues and with the manufacturing team to resolve DRC-related challenges. Creating and updating flows/methodologies in collaboration with architects and circuit design engineering teams. The Impact You Will Have: Accelerating the integration of next-generation intelligent in-chip sensors and analytics into cutting-edge technology products. Optimizing performance, power, area, schedule, and yield across semiconductor lifecycle stages. Enhancing product reliability and differentiation in the market while reducing risk. Driving innovation in physical verification and signoff design methodologies and tools. Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You ll Need: Educational Background : BS/B.Tech or MS/M.Tech in Electrical Engineering with 5+ years of relevant industry experience. Technical Expertise : Strong experience in physical verification and signoff, including DRC, LVS, DFM, ANT, ERC, ESD, EM, and PERC cleaning. Proficiency with digital design tools from any EDA vendor, preferably Synopsys tools like FC and ICV. Solid understanding of physical design, physical verification, and signoff concepts. Proven track record of successful physical verification closure and tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, 2nm). Experience with design methodologies, including developing custom scripts and enhancing flows for better execution (TCL/PERL scripting required). Additional Skills : Exposure to floorplan and PnR flows and tools such as ICC2/FC/Innovus is an added advantage. Good understanding of reliability physics, including EM, ESD, crosstalk, shielding, latch-up, and deep sub-micron challenges. Who You Are: Proactive and detail-oriented with excellent problem-solving skills. Adept at working independently and providing physical verification and signoff solutions. A strong communicator and teamer, capable of collaborating effectively with diverse teams. An innovative thinker with a passion for technology and continuous improvement. Committed to delivering high-quality results and achieving project goals. The Team You ll Be A Part Of: You will join a dynamic and collaborative team of engineers focused on developing cutting-edge semiconductor solutions. The team works on advanced physical verification methodologies, physical design, and signoff processes, driving innovation and excellence in the development of next-generation technology products. Together, you will tackle complex challenges, push the boundaries of technology, and contribute to the success of Synopsys industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply As an applicant your resume, skills, and experience are being reviewed for consideration. Phone Screen Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. Interview You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

In This Role, Your Responsibilities Will Be: Analyze the monthly profit and loss account of this business unit and support the completion of the monthly financial submission to management. Relate variances at the sub-business unit level and provide management insight on business health and recommend improvement and corrective action. Partner with business leaders to provide insightful information on cost position to help strategic business decisions. Costing review and ensure the rate is allocated accurately and its assumption is appropriate. Manage Fixed assets are spent within budgeted limits, capitalized on time per policy, support physical tagging of assets, and coordinate for periodic physical verification. Review standard cost and annual revision. Perform cost variance analysis, supervise and manage stock movement, and valuation for inventory. Coordinate for inventory physical verification and cycle count. Lead and take charge of statutory audits, internal control, and compliance with the company s policies and procedures. Timely completion of cost audit. Ensure that all tax returns, tax declarations, and other reporting requirements are met timely. Who You Are: Good business insight and strong analytical skills Strong written and verbal communication skills. To work both as an individual contributor and be able to manage a team. Be comfortable working in a matrix organization structure, reporting across geographies, legal entities, and functions. To work in a fast-paced team environment to meet timelines. Experience coordinating with cross-functional departments like sales, HR, logistics, and external consultants. Strong work ethics For This Role, You Will Need: You serve as strong business support to drive the site performances together with other functional leaders. You are one of the gatekeepers for compliance with Indias statutory requirements and Emerson s internal policies and procedures. You run timelines rigorously and contribute to strengthening the financial backbone of the business. Preferred Qualifications That Set You Apart: Qualified Chartered accountant or equivalent professional qualification Minimum 7 years of working experience in finance or accounting with validated track records. Solid Understanding in a manufacturing environment Experience in the area of financial reporting under Indian GAAP and US GAAP in a manufacturing organization. Our Culture & Commitment to You: At Emerson, we prioritize a workplace where every employee is valued, respected, and empowered to grow. We foster an environment that encourages innovation, collaboration, and diverse perspectives because we know that great ideas come from great teams. Our commitment to ongoing career development and growing an inclusive culture ensures you have the support to thrive. Whether through mentorship, training, or leadership opportunities, we invest in your success so you can make a lasting impact. We believe diverse teams working together are key to driving growth and delivering business results. We recognize the importance of employee well-being. We prioritize providing competitive benefits plans, a variety of medical insurance plans, an Employee Assistance Program, employee resource groups, recognition, and much more. Our culture offers flexible time-off plans, including paid parental leave (maternal and paternal), vacation, and holiday leave.

Provide technical and managerial Leadership to a PD team for a SoC Chip development owning partitions and full-chip from synthesis to place and route through all sign-off including timing signoff, physical verification, EMIR signoff, and formal verification. Influence tools, flows, and overall design methodology in design construction, signoff, and optimization. Work closely with architecture/RTL/DFT/DV/Package development teams. Be a technology expert in the area of Physical Design with in the team and business Unit. Minimum Qualifications 10 to 15 years of experience in Physical Design. Proven experience in implementing designs through synthesis, Floorplanning, place and route, extraction, timing, and physical verification. Technically lead a team of PD engineers on the Physical Design activities of complex SoCs. Strong understanding of constraints generation, timing optimization, and timing closure and STA. Strong technical problem solving and debugging ability Experience in EDA tools related to Place and route, Synthesis, Physical Verification , STA etc. Proficient understanding of CTS and different clock building techniques Experience with multi-clock, multi-power-domain design, UPF etc Experience in IP integration (memories, IO s, embedded processors, hard macros, Analog IP) Knowledge of Microelectronics concepts Scripting skills in Python, Tcl, C etc Ability to collaborate and work directly with the tool vendors to resolve tools bugs, as well as implement the required improvements Great communication and teamwork skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 1-3 yrs years of experience in Physical Design/Implementation

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Qualcomm is a company of inventors seeking to revolutionize the CPU market in an age of new possibilities. Are you interested in joining Qualcomm’s high performance CPU team as an SRAM Mask Layout DesignerYou will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. As a Mask Layout Designer, you will develop block or macro level layouts and floorplans for high performance custom memories according to project requirements, specifications, and design schematics. Minimum qualifications 5+ years of experience and a high school diploma or equivalent OR 5+ years experience and BS in Electrical Engineering OR 3+ years experience and MS in Electrical Engineering Direct experience with custom SRAM layout Experience in industry standard custom design tools and flows. Knowledge of leading-edge FinFET and/or nanosheet processes (5nm or newer). Experience in Layout design of library cells, datapaths, memories in deep sub-micron technologies. Knowledge of all aspects of Layout floorplanning and hierarchical assembly. Knowledge of Cadence Virtuoso and Calibre LVS/DRC. Preferred qualifications Good understanding of device parasitics and reliability considerations during layout. Good understanding of critical circuits and layout styles. Ability to write Skill code for layout automation. Knowledge of improving EMIR in layout. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Roles and Responsibilities Design layout for custom memories and other digital circuits based on provided schematics. Read and interpret design rule manuals to create optimal and correct layout. Own the entire layout process from initial floorplanning to memory construction to physical verification. Use industry standard verification tools to validate LVS, DRC, ERC etc. Interpret the results from the verification suite and perform layout fixes as needed. Provide layout fixes as directed by the circuit design engineers. Work independently and execute memory layout with little supervision. Provide realistic schedules for layout completion. Provide insight into strategic decisions regarding memory layout and

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Physical Design CAD engineer, you will build and support the world’s best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. Roles and Responsibilities Develop, integrate and release new features in our high-performance place-and-route CAD flow Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain, support and debug implementation flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA. Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role High level of proficiency in Tcl as well as Python Experience with automation Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Solid understanding of digital design, timing analysis and physical verification Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience 7 to 10 years Physical design of block level with full understanding of PnR cycle. Good understanding of Physical design fundamentals Good hands-on experience on industry standard pnr tools like ICC2/Innovus Good understanding on signoff tool like Prime time , Redhawk and calibre Should be able to guide junior engineers in resolving technical issues. Tools ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS ScriptingTCL, Perl

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Experience Required8+ Years (A must) Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages – TCL, Perl, Awk Basic knowledge of device phy STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs Qualcomm Hexagon DSP IP's . Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Role * Physical Design Life cycle of chip development, especially Floorplanning and PnR * Hands on PD execution at block/SoC level along with PPA improvements * Strong understanding of the technology and PD Flow Methodology enablement. * Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area/power/performance/convergence), develop plans and deploy/support them * Provide tool support and issue debugging services to physical design team engineers across various sites * Develop and maintain 3rd party tool integration and productivity enhancement routines * Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions. Skill Set * Strong programming experience & Proficiency in Python/Tcl/C++ * Understand physical design flows using Innovus/fc/icc2 tools * Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory * Basic understanding of Timing/Formal verification/Physical verification/extraction are desired * Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory*

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.This requirement is for DDR PD team for Bangalore. Number of openings: Sr. Lead (6 to 8 years) 2 Staff (8 to 10 years) 1 Sr Staff (10 to 12 years) 1 Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages – TCL, Perl, Awk Basic knowledge of device phy STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs Qualcomm Hexagon DSP IP's . Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelor’s or Master’s degree from a top-tier institute. 6-8 years of experience in physical design from product-based companies. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in complete Netlist2GDSFloorplan, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Hand on experience in lower technology nodes. Job : Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA. Managing and driving a small team for project execution and PPA targets

We Are Hiring: Principal Engineers Chip Design (Back End / Front End / Analog IP/IC) Preferred Skills and Experience: Minimum 1+ years of experience in Project Management (Waterfall and Agile Hybrid methodology) Exposure to continuous improvement and cross-functional collaboration Educational Qualifications: Master's degree in VLSI Design from reputed institutes (IITs/NITs preferred) Bachelor's in Electronics and Communication or a related field 1. Job Title: Principal Engineer – Chip Design Back End Required Skills & Experience: Minimum 8+ years of strong experience in backend flows for MCU or low-power SoC designs Leadership experience with DFT, Physical Design, and Formal Verification teams Exposure to Frontend and Analog design processes Ability to collaborate effectively across functional teams Experience in product support during both pre- and post-production stages (including RMA support) 2. Job Title: Principal Engineer – Chip Design Front End Required Skills & Experience: Minimum 8+ years of experience in system architecture for ARM-based MCU product development Expertise in RTL design, RTL coding, and RTL integration Strong debugging and design capabilities Experience leading verification teams, including static and dynamic verification, test management (UPF, GLN, Test Modes) Familiarity with industry-standard EDA tools (e.g., Synopsys for LINT, CDC, SDC validation, and power analysis) Exposure to Backend and Analog design processes Cross-functional collaboration with PD, DFT, and STA teams for timing and power closure Experience in pre- and post-production product support and RMA handling 3. Job Title: Principal Engineer – Analog IP/IC Design Required Skills & Experience: Minimum 8+ years of experience in custom analog/mixed-signal IC design Proficiency in variation-aware design, verification planning, and analog layout parasitic extraction (LPE) Hands-on experience with analog/mixed-signal EDA tools (e.g., Cadence, Synopsys) Strong debugging and design validation skills Product support experience across development lifecycle, including RMA stage

Physical Deisgn Lea LocationBangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experienceon Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl Well versed with timing constraints, STA and timing closure. Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify designs or repair equipment as needed e. Allocates modules for testing and verification and reviews data and project documentation f. Provides guidance on technical escalations and review regression testing data g. Prepares documentation containing information such as test case and product scripts for IP and publishes it to the client for feedback and review h. Ensures all project documentation is complete and uploaded as per technical specifications required by the client 2. Provide customer support & governance of VLSI components & hardware systems a. Identify and recommend system improvements to improve technical performance b. Inspect VLSI components & hardware systems to ensure compliance with all applicable regulations and safety standards c. Be the first point of contact to provide technical support to client and help debug specific, difficult in-service engineering problems d. Evaluate operational systems, prototypes and proposals and recommend repair or design modifications based on factors such as environment, service, cost, and system capabilities 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: VLSI Physical Place and Route. Experience5-8 Years.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What youll be doing: In this position, you will expected to lead all block/chip level PD activities. PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM, IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges. Help team members in debugging tool/design related issues. Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. What we need to see: BE/BTECH/MTECH, or equivalent experience. 4+ years of experience in Physical Design. Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure. Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. Ability to multi-task and flexibility to work in global environment. Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred.

ENSURE ALL MATERIALS BOARD REELS ARE KEPT IN A PROPER AREA. APPLY THE FIFO METHOD. ALL INVENTORY SHOULD BE MAINTAINED IN EXCEL CONSUMPTION AND PURCHASES SHOULD BE ADJUSTED ON A DAY-TO-DAY BASIS. NEED TO ENSURE PHYSICALLY MATERIAL IS HANDED OVER.

Ensuring accurate and timely Monthly & Quarterly Closing- maintaining Balance Sheet Integrity Timely & Accurate closure of books of Accounts. General Ledger closing as per timelines with all completeness. Trail Balance Review & Analysis with detail remarks for major variances with respect to prior periods, forecasts and AOP. Ensuring Timely & accurate delivery of FR closing pack. Proper Schedules & back ups for each Balance sheet GL line items with ageing. Major movement of any GLs would be tied up with all necessary approvals, within budgets & with proper justifications. Ensure adequate backups are available for all accounting information and necessary reconcilliations and validations and verifications have been carried on and documented to satisfy the requirements of Balance Sheet integrity. Provide timely and accurate information for Schedule VI and notes to accounts on a quarterly basis. Coordination for Circle Audit. Ensuring all submission of details & schedules to Auditors(Statutory, Concurrent & Internal) Providing Resolution/remarks for all the queries raised by Auditor. Ensuring there are no audit points and timely closure of the same if there are any observations Co ordination with other functions for smooth closure of Internal Audits. AOP Preparation & Budget Tracking to plan the circle related activities Preparation of Annual Operating Plantion plan activity including coordination for inputs from various functions in circle and Corporate, collating and analysing the same Submission of the AOP and related information as per guidelines and within agreed timelines Continuous monitoring of the AOP and control & tracking with respect to different categories like Opex/Capex. Generate reports to highlight concerns areas and discuss with various stakeholders to devise corrective action plans. Fixed Assets Recording, Monitoring and Custodianship Ensure accurate and timely recording of transactions relating to Fixed Assets. Drive and monitor control mechanisms like physical verification, systems review etc. to ensure adequate controls Monitor Capex efficiency, adherance to Capex budgets, control over SRN material and ensure timely recording of site to site movements Coordinate with other functional heads to ensure an adequate health assessment of assets so that any provisions or write offs or Insurance claims are timely recorded/lodged. Coordinate with central FA team for making available all necessary information for concluding audits and for effective decision making and analysis by Circle Leadership team. Management Information Prepare and ensure timely delivery of accurate information around Site wise profitability, profitability Forecasts, Budget monitoring, Target achievement, various circle KRAs, and other adhoc information requirements from Circle Management team. Act as the main coordinator for any financial and non financial reviews for the Circle Qualification : Minimum Educational Qualifications to perform this job Chartered accountant Knowledge Required Expertise in Finalization of Accounts, IGAAP, Companies Act, Schedules VI Skills / Competencies Should have a fair understanding of the business and must have prior experience of working in ERP systems. Ability to present vast information in a concise form so as to draw attention to real issues.Exposure to IGAAP and Big 4 audit processes. Relevant Experience (Functions, roles, duration) Minimum 5 Years of Total Experience in Finance & accounts including at least 2-3 years of experience in preparation & finalization of Accounts. Hiring Pool (industries, specific organizations from where targeted) Any Industry

Coordinate with store warehouse & procurement Dept Surprise physical stock verification Preparation of audit working & Report documentation Expert in Inventory Management, ERP, Tally work independently, ready to travel Identify shrinkage & fraud

As an Implementation Engineer in Arms Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible. At Arm, our work goes beyond multiple divisions where we'drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC Analyze design timing, area and power to help improve the quality of ARM IP Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience : Bachelors or masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 8 to 12 Years years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh. Nice To Have Skills and Experience : Knowledge around Arm based CPUs and SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding! Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises

As an Implementation Engineer in Arms Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible. Responsibilities: Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC Analyze design timing, area and power to help improve the quality of ARM IP Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience : Bachelors or masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 8 to 12 Years years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh. Nice To Have Skills and Experience : Knowledge around Arm based CPUs and SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises

Working experience in Physical Design implementation areas including Synthesis, LEC, and PnR as we'll as good exposure to signoff areas, particularly power, timing, and IR signoff. Job Description Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification , and taking blocks to the closure. Design Application Engineering (DAE ) will be responsible for supporting project teams using Infineon Design System (Flows, Design Package & Design assistance). You will be the first point of contact for project teams in case of issues and will work to achieve the highest customer interaction. Responsible for automation of manual processes (including design flow/design package qualification mechanisms, generation of test reports/dashboards etc) and providing automation requirements for reducing manual steps in qualification. The candidate will have an internal drive to work with design and EDA vendors to solve issues and adopt new flows. The candidate should have reasonable ability to automate design work by means of script programming, eg Tcl/tk, Perl or Python. Your Profile The candidate should have a minimum of 6 years of relevant working experience in Physical Design implementation areas including Synthesis, LEC, and PnR as we'll as good exposure to signoff areas, particularly power, timing, and IR signoff. One should have a deep understanding of and be able to be cater to design concerns across semi-custom design flows, including RTL analysis, synthesis, LEC, Place and Route, STA, EM/IR, and physical verification. One should be able to identify flow gaps and provide automation on need base to perform all design activities in the most efficient and correct-by-construction way. One should be able to evaluate solutions from multiple available options and be able to perform trade-offs between technical features. Analyse the results and any inconsistency issues to be reports via bug tracking system. One will work with R&D in Infineon globally and EDA tool vendors to resolve issues across semi-custom design flows. One will coordinate with IT and EDA tool license teams to provide an infrastructure aligned with project needs. One should have exposure to basic version management using any of Clearcase / Perforce / Cliosoft / Git. You should possess excellent communication skills to interact effectively with peers and customers in a clear and honest manner with consistent and open to learning new technical areas if the need arises. You should define and monitor key test metrics, build regression status reporting dashboard, Develop and execute QA test plans, verification methodology & test strategies for digital block/chip level to maximize the coverage of features/methodology supported in the technologies/Design Flows.