1022 Physical Verification Jobs - Page 9

Your role and responsibilities -Lead the Architecture, Design and development of processor MMU (Memory management unit) for high- performance IBM Systems. - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the MMU feature enhancements. - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. Required education Bachelor...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Verification Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :Full chip / Subsystem / Block level Physical verification for deep submicron technology 7nm and belowExpertise in LVS, ERC, PERC, DRC, Antenna, DFM, DensityDeep understanding of ESD analysisGood exposure to BUMP and RDL planningHands on experience with Innovus / Fusion compiler ...

As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- 1) Place and Route, CTS, Routability analysis with respect to congestion 2) we'll versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) 3) Meeting RC requirements for manual/special signals 4) Good understanding of Calibre DRC/LVS/DFM, DFY, ERC and ESD latchup 5) Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release, 6) Good scripting knowledge perl and TCL, familiar with Caliber, Innovus, 7) Understanding of VLSI fabrication process, 8) Implementing timing ECOs Implementing IR drop fixes, RC extraction, signal EM fixes, and Trans,...

Required skills: He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engrs. Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Timing...

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- 1) Place and Route, CTS, Routablity analysis with respect to congestion. 2) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) 3) Meeting RC requirements for manual/special signals 4) Good understanding of calibre DRC/LVS/DFM,DFY, ERC and ESD latchup. 5) Responsible for all the integrity checks (chip-finis...

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job description, As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :- 1) Place and Route, CTS, Routablity analysis with respect to congestion. 2) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout) 3) Meeting RC requirements for manual/special signals 4) Good understanding of calibre DRC/LVS/DFM,DFY, ERC and ESD latchup. 5) Responsible for all the integrity checks (chip-finis...

Skills: VLE, Cadence Software, VLX, Calibre, DRC, LVS,. Layout Designer _ Hyderabad (5 to 8 Years. Description. Role and Responsibilities. Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work....

SENIOR PHYSICAL DESIGN ENGINEER SENIOR PHYSICAL DESIGN ENGINEER SmartSoC is looking for smart and enterprising Physical Designer Engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. This role will involve Physical design at the block and chip level of complex designs in the latest technologies. Desired Skills and Experience- 3 – 10 years relevant experience Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background of Floor planning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing an...

Lead Analog Layout Engineer Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shel...

Analog Layout Engineer Analog Layout Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech ESSENTIAL DUTIES AND RESPONSIBILITIES: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job C...

Job Title: Branch Auditor Experience Required: 4 + Years Location: Bengaluru (Neelamangala) Department: Internal Audit Reporting To: Internal Audit Head Key Responsibilities: Conduct physical verification of inventory at base and branch locations across India. Perform comprehensive reviews of branch operations , ensuring compliance with internal policies and procedures. Undertake market visits to assess operational effectiveness and gather field insights. Carry out inspections of LED bulb production and inventory . Prepare and finalize Physical Verification (PV) and Branch Operations Reports with actionable insights. Ensure minimum 15 days of travel per month to various branch locations. Col...

Job Title: Branch Auditor Experience Required: Minimum 4 Years Location: Lucknow, Transport Nagar, Kanpur Road Department: Internal Audit Reporting To: Internal Audit Head Key Responsibilities: Conduct physical verification of inventory at base and branch locations across India. Perform comprehensive reviews of branch operations , ensuring compliance with internal policies and procedures. Undertake market visits to assess operational effectiveness and gather field insights. Carry out inspections of LED bulb production and inventory . Prepare and finalize Physical Verification (PV) and Branch Operations Reports with actionable insights. Ensure minimum 15 days of travel per month to various br...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engine...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your typical day will involve collaborating with team members to ensure the successful imple...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your typical day will involve collaborating with team members to ensure the successful imple...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, your typical day involves analyzing, designing, coding, and testing various components of application code across multiple clients. You will engage in maintenance and enhancement tasks, ensuring that the software remains efficient and effective. Coll...

Role Overview: As an Assistant Vice President - Business Expense (BX) Cost Controller Center of Excellence (CoE) at Barclays, you will lead the evolution of the digital landscape by driving innovation and excellence. Your primary focus will be on utilizing cutting-edge technology to transform digital offerings and ensure unparalleled customer experiences. Key Responsibilities: - Ensure accuracy and transparency in financial reporting as per governance requirements, including documentation and certification of controls. - Prepare asset-related disclosures and schedules. - Ensure timely capitalization of projects and accurate CWIP monitoring. - Ensure adherence to Economic Transfer Agreements ...

Own and execute all aspects of the physical design flow, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification (LVS/DRC). Drive timing closure using STA tools, addressing violations across multiple PVT corners. Perform IR drop and EM analysis and implement fixes to ensure power integrity compliance. Collaborate cross-functionally with RTL, DFT, packaging, and manufacturing teams to achieve optimal design quality and performance. Debug PnR, DRC/LVS, and timing flow issues, providing detailed root-cause analysis and effective solutions. Contribute to flow enhancements and automation initiatives to improve design quality, efficiency, ...

Hi Greetings!! Immediate openings for Leadsoc technologies pvt ltd. Role & responsibilities Expertise in Calibre DRC flows, DRC fixes. Preferred candidate profile 3+ PV Engineer Bangalore Immediate to 30 days Interested candidates can send updated resumes to basheer.unnisa@leadsoc.com or Contact HR Basheera- 8310938311.

Position: Senior VCLP Physical Design Engineer (SI50FT RM 3657) Professional Summary : Senior VCLP Physical Design Engineer with 5+ Years of Experience. An accomplished engineering professional possesses expertise in VCLP And physical design implementation at lower tech nodes with high performance , Multi voltage design, place route, Power Opt, STA, physical verification and performance management. Skilled in determining the functional processes necessary to meet organizational goals; facilitating successful people management, and operations, and identifying trends Physical Design Implementation. A career-motivated and passionate individual with solid experience in the areas of VCLP and phys...

Analog / Custom Layout Design Engineer (TSMC 3nm | FinFET | Cadence | Calibre) Experience: 4 to 8 Years Location: Hyderabad Job Description: We are seeking a highly skilled Analog / Custom Layout Design Engineer to drive the design and development of critical analog, mixed-signal, and custom digital layouts , supporting full-chip level integration in advanced FinFET process technologies. You will be responsible for end-to-end layout execution from schematic translation and floor planning to verification and final sign-off — while collaborating closely with circuit designers, verification engineers, and project leads. Key Responsibilities: Design, develop, and implement analog, mixed-signal, ...

Location: Bangalore, Hyderabad, Noida, and Coimbatore. Skills: Soc level floorplanning, partitioning, timing budget generations, power planning, SOC PnR, CTS, block integration Handling timing closure of high frequency blocks. Expertise in signoff closure Timing with SI and OCV, Power, IR and physical verification at both block and chip level. Understanding constraints and fixing techniques. Experience in physical verification Understanding SI prevention, fixing methodology and implementation. Proficient in Synopsys ICC or Cadence or Mentor Olympus and Atoptech tool set. Experience in Design Automation and UNIX system. Experience in Tcl/ PERL is a plus. Primary Skills: Able to handle Soc PNR...

We are looking for a skilled Senior Manager - Physical Design with 10-15 years of experience to lead our team in Bangalore, Hyderabad, Noida, Coimbatore. The ideal candidate will have a strong background in physical design and excellent leadership skills. Roles and Responsibility Manage and lead a team of physical design engineers to achieve project goals. Develop and implement automation scripts for physical design methodologies. Collaborate with front-end engineers to resolve timing and power issues. Evaluate new tools and drive power reduction of designs. Perform floorplanning and time budgeting for successful project execution. Ensure timely completion of projects by managing resources e...

As a Virtuoso Layout Engineer at Cadence, your main responsibility will be to meet with customers/prospects to identify and qualify opportunities. You will need to work out agreeable evaluation criteria, run through the evaluation process, and convert these opportunities into business. Your role will also involve assisting customers in deploying the tool and ensuring its smooth operation in production. Having a strong understanding of customer flow and excellent analytical skills to resolve issues impacting production schedules will be crucial. Handson knowledge of Advance Node layout and design rules would be considered a plus. Your job will require close interaction with the R&D and Produc...

Role Overview: You are required to lead the end-to-end VLSI components and hardware systems, providing customer support and governance of VLSI components and hardware systems, and managing the team effectively. Key Responsibilities: - Design, analyze, develop, modify, and evaluate VLSI components and hardware systems - Determine architecture and logic design verification through software for component and system simulation - Conduct system evaluations, make appropriate recommendations, and review data and project documentation - Identify and recommend system improvements for better technical performance - Inspect VLSI components and hardware systems for compliance with regulations and safety...