812 Physical Verification Jobs - Page 8

Working experience in Physical Design implementation areas including Synthesis, LEC, and PnR as well as good exposure to signoff areas, particularly power, timing, and IR signoff. Job Description In your new role you will: Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Design Application Engineering (DAE) will be responsible for supporting project teams using Infineon Design System (Flows, Design Package & Design assistance). You will be the first point of contact for project teams in case of issues and will...

Responsible for high-performance microprocessor blocks RTL to GDSII implementation Perform block-level synthesis, floor-planning, placement, and routing. Close the design to meet timing, power budget, and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8-12 years of industry experience in physical design methodology. Good knowledge and hands-on experience in physical design methodology, which includes logic synthesis, placement, clock tree synthesis, and routing. Should be knowledgeable ...

You are seeking a Digital/Memory Mask Design Engineer to join a dynamic team managing complex high-speed digital memory circuit designs at NVIDIA. As a part of the team, you will be involved in reinventing the field of artificial intelligence and enhancing human creativity and intelligence. You will work in a diverse and supportive environment where delivering your best work is encouraged. Your responsibilities will include: - Executing IC layout for innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes of 3nm, 5nm, 7nm, and lower nodes using industry-standard methodologies. - Leading the architecture and layout design of critical memory subsystems, ...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com. Basic Qualifications Strong academic and technical background in electrical engineering. A Bachelor's de...

Job Summary: The Store Incharge is responsible for the overall management of the store, including inventory control, material handling, record-keeping, and ensuring timely availability of materials for smooth operations. The role involves supervising staff, maintaining stock levels, and ensuring proper documentation of all inward and outward materials. Key Responsibilities: Manage and oversee daily store operations and inventory movement. Receive, inspect, and verify all incoming materials as per purchase orders and invoices. Maintain accurate stock records (inward, outward, and balance) in registers/software. Issue materials to departments/sites against approved requisitions. Ensure proper ...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do thei...

As a Qualcomm Hardware Engineer, your role will involve planning, designing, optimizing, verifying, and testing electronic systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. **Key Responsibilities:** - Participating in ASIC development projects with a focus on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. - Creating design experiments, conducting detailed PPA comparison analysis, collaborating with various teams for optimizati...

As a Memory Layout Engineer at our company, you will play a crucial role in designing and integrating layouts for advanced memory blocks across leading-edge process technologies. Your primary responsibilities will include: - Designing layouts for essential memory components such as Control and Digital logic, Sense amplifiers, Bit-cell arrays, and Decoders. - Working with advanced process nodes like 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, and FinFET technologies. - Developing memory compilers, addressing layout-related issues, and ensuring optimization. - Proficiency in Routing Congestion, Physical Verification in Custom Layout. - Knowledge of verification checks like DRC, LVS, ERC, Antenna, LPE, DF...

You should have at least 3+ years of relevant experience in SoC Physical design, with a focus on multiple technology nodes including 5nm for TSMC and other foundries. Your expertise should include hands-on P&R skills, particularly in ICC/Innovus. You must possess expert knowledge in all aspects of Physical Design (PD) from Synthesis to GDSII, with a strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure. - Experience in taping out multiple chips and working at the top level in the latest technology nodes will be highly beneficial. - Collaboration with CAD, Methodology & IP teams for PD implementation is critical, r...

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems. You will work on a variety of systems, including circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems. Your role will involve developing cutting-edge products and collaborating with cross-functional teams to ensure that the solutions meet performance requirements and contribute to the projects" success. Key Responsibilities: - Plan, design, optimize, verify, and test electronic systems - Work on circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems - Develop cu...

Handling Purchase Activity for Entire University, timely delivery of material, Daily PR Status updation on portal , record keeping , Physical verification process, Preparing MIS report. Follow up with the vendor for delivering the material.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engine...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

About The Role Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Lead end to end VLSI components & hardware systems a. Design, analyze, develop, modify and evaluate the VLSI components and hardware systems b. Determine architecture and logic design verification through software developed for component and system simulation c. Analyze designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions d. Conduct system evaluations and make appropriate recommendations to modify des...

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

Graduate/ Postgraduate in Forest Management, Forestry, Wood Science and QMS, ISO 9001:2015. Experience- Minimum 1 2-year. Skills required- High level of process orientation, eye-for-detail/ observation power and analytical skills clubbed with reasoning ability. Ability to take up responsibilities and conduct physical verification. Effective communication and presentation skills with ability to keep the audience engaged. Hands-on in documenting, observations and finding. Proficiency in MS-Office comprising of MS Word, Power Point and Excel Ability to grow business and retain the existing clients. Willing to travel to multiple locations. Job Responsibilities- Coordinate with client and Head of...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

You will be responsible for the further development of concepts and methods for the EDA design environments with focus on analog / mixed signal CAD flows. Expert level proficiency in one or more of the programming/scripting languages SKILL, Python, Unix, Perl and TCL. Expertise in Virtuoso suite of tools and Analog Design environment (finesim/PrimeSim) Solid understanding of Calibre Physical Verification decks(SVRF) and ICV LVS decks with hands-n experience in integrating various PV flows in CAD environment. Solid experience in Layout Automation and Utilities development in Cadence SKILL/SKILL++. Development and validation of PV tools and flows like parasitic extraction, EMIR drop and substr...

Person should have complete end-end knowledge of the Netlist- Gds Tapeout methodology preferably at a chip level Must have hands on experience of working on multiple chips in the above methodology Must have lead a team in the above methodology May not be hands-on But Should have in-depth understanding of the timing concepts and requirements at Synthesis level and it s effect and relation with Place and route and timing closure May not be hands-on but should have good knowledge of nuances of timing closure in STA Must have hands-on experience of working on Physical verification and must have lead a team to Tapeout Should have good communication skills both written and verbal Experience of wor...

General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, El...

[ Location: NOIDA] Exp: 06-15Y We are seeking a highly skilled & experienced PDN & PV expert to join our Flows & Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope of Responsibilities: As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define PDN & PV flow & methodology to meet SoC & IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools an...

Role Overview: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. This position will focus on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with an emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. Key Responsibilities: - Drive floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA - Engage in cross-fun...

As a PHY Hardening Engineer at Ampere, you will have a crucial role in developing cutting-edge expertise in high-speed digital design. You will collaborate with various teams, including architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups. Your tasks will involve optimizing layouts, ensuring signal and power integrity, and performing chip-level physical design tasks. Your expertise in managing high-speed signals and advanced packaging techniques will be vital in delivering reliable designs meeting timing, power, and manufacturability requirements. Key Responsibilities: - Collaborate with cross-functional teams to optimize layouts and ensure signal and...

Experience on RTL2GDS Implementation i.e. Synthesis, Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and lower tech nodes like 7nm, 6nm & 5nm. Should have experience in handling high frequency partitions & memory dominated designs. Should have experience on programming in Tcl/Tk/Perl. Well versed with timing constraints, STA and timing closure. Should have worked on minimum 3 tapeouts. Should have hands-on experience on Hierarchical level PV & signoff closure Tools: Innovus, Tempus Experience Range : 5 - 15 years Primary Skills : Physical Design, CTS, STA & Physical Verification.

Dear Candidate's find the below details & JD Experience: 3-5 years Notice period: immediate - 15 days Location: Hyderabad interview: 2-3 rounds Job Description: - Develop standard cell layouts and detailed drawings from schematics - Perform physical verification and layout optimization - Collaborate with design engineering and CAD teams - Ensure design rules, yield, and reliability requirements are met. - Expertise in Cadence tools, including Virtuoso and Caliber - Strong understanding of layout fundamentals and physical verification - Excellent problem-solving and communication skills. Interested Designers can share their Updated resume at kalyanreddy.k@acesoftlabs.com Note: matching profil...