401 Physical Verification Jobs - Page 13

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux- Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: As a Staff/Senior Staff SoC Physical Verification Engineer, you will be responsible for leading and executing full-chip and block-level physical verification (PV) for advanced SoC designs. You will collaborate with cross-functional teams to ensure design integrity, manufacturability, and compliance with foundry rules across multiple technology nodes (e.g., 7nm, 5nm, 3nm). Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Key Responsibilities: Own and drive physical verification (LVS, DRC, ERC, PERC, Antenna, DFM) at block and top levels. Collaborate with Physical Design (PD), RTL, and CAD teams to resolve PV issues and ensure sign-off quality. Analyze and debug PV violations using tools like Calibre, ICV, and IC Validator. Work on ESD routing, bump/RDL planning, and padring integration. Develop and refine PV flows and methodologies in collaboration with CAD teams. Mentor junior engineers and lead PV closure for complex SoC programs. Interface with foundries for rule deck updates and tapeout readiness. Required Skills & Qualifications: B.E./B.Tech or M.E./M.Tech in Electronics, VLSI, or related field. 7"“14 years of hands-on experience in SoC physical verification. Strong expertise in Calibre, ICV, ICC2, Fusion Compiler, and Innovus. Deep understanding of DRC, LVS, ERC, PERC, Antenna, and density checks. Experience with advanced nodes (7nm and below) and FinFET technologies. Familiarity with scripting (TCL, Perl, Python) for automation and debugging. Exposure to ESD, latch-up, IR drop, and EM analysis. Excellent problem-solving, communication, and leadership skills. Preferred Qualifications: Experience with Intel, TSMC, or Samsung foundry rule decks. Knowledge of RTL-to-GDSII flow and ECO implementation. Prior experience in customer-facing or cross-site collaboration roles.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 12+ years of experience in Physical Design/Implementation Minimum Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems "which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl /Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/ Masters degree in Electrical /Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. Qualcomm IPCAD team is developing products and features for Qualcomms in-house validation and release platform for IPs for the next generation System-on-chip (SoC) for smartphones, laptops and other categories. This tool provides libraries and IPs a platform to validate the data before they are integrated with SoC. It also provides release vehicles to make IPs available for SoC in the most seamless way. We are seeking ambitious, bright and innovative engineers with experience in software design, CAD and implementation. Job activities span the whole product life cycle from early requirement gathering to in-house deployment. The environment is fast-paced and requires cross-functional interaction on a daily basis so good communication, planning and execution skills are a must. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Responsibility include : The responsibilities of this role include: Interacting with SoC and IP to understand requirement, define and implement quality enforcing checks. Involved in analyzing field issues and proposing new quality requirements. Making decisions that are moderate in impact; errors may have financial impact or effect on projects, operations, or customer relationships; errors may require involvement beyond immediate work group to correct. Using verbal and written communication skills to convey complex and/or detailed information to multiple individuals/audiences with differing knowledge levels. May require strong negotiation and influence, communication to large groups or high-level constituents. Completing tasks that do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach; mistakes may result in significant rework. Exercising substantial creativity to innovate new processes, procedures, or work products within guidelines or to achieve established objectives. Working independently with little supervision. Minimum Qualifications Bachelors degree in Electronics engineering, Information Systems, Computer Science, or related field 3-7 years VLSI or related work experience Experience in programming using Python. Preferred Qualifications The person hired in to this role will be contributing to IP validation toolset. 3+ years in software development using Python/Perl. Strong development skill in Python is must. Good understanding of the VLSI design flow in terms of physical implementation, physical verification, signoff. Candidate can have depth in one domain and readiness to pick up another domain. 3+ years in backend CAD flows for STA, DRC/LVS/ERC Working experience in any of STA, DRC, LVS is a plus. Good knowledge on both Front End and Back End ASIC Design flow Basic understanding of Digital Design, Verilog and System Verilog, Assertions Exposure to RTL quality checks like Lint, CDC, Synth, Compilation and Elaboration etc. Good documentation skills. Experience in RTL Design, IP Development or Verification is a plus

In this role, you will work closely with layout, DRC/LVS, and tapeout teams to perform physical signoff checks, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checks (ERC) using industry-standard EDA tools

Introduction Physical design team is responsible for designing high performance microprocessor blocks for IBM Power and z mainframe servers. Your role and responsibilities Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing Close the design to meet timing, power budget and area Implement ECO's to address functional bugs and timing violations Team player, with good problem solving and communication skills Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 58 years industry experience in physical design methodology Good knowledge and hands-on experience in physical design methodology which include logic synthesis, placement, clock tree synthesis, routing Should be knowledgeable in physical verification (LVS, DRC.. etc), Noise analysis, Power analysis and electro migration Team player with good problem solving skills, communication skills and leadership skills Preferred technical and professional experience Automation skills in PYTHON, PERL, SKILL and/or TCL

The Opportunity Were looking for the Wavemakers of tomorrow. Custom Layout / High-Speed Analog Layout Engineer Alphawave IP builds industry-leading wired connectivity solutions that enable data to travel faster, more reliably, and with higher performance at lower power. Our technology is embedded in leading-edge semiconductors built to power global network and computer systems. It is an essential part of the core infrastructure enabling next generation services in data centers, artificial intelligence, 5G wireless infrastructure, data networking, autonomous vehicles, and solid-state storage. The Opportunity The Alphawave IP team combines technologists from different disciplines who come together with a shared passion for electronics, software, and communication technology. We look for individuals with a deep desire to build great products and we value collaboration, curiosity, and a commitment to solving hard problems. The Alphawave Custom Layout team is composed of a group of highly technical, innovative, and passionate engineers, collaborating to develop the analog layouts and architectures for our world class high-speed SerDes IP s. What You ll Do Custom analog layout design for industry leading high speed Serdes architectures Working in leading edge semiconductor nodes and cad tools including latest 3nm node Detailed collaboration in optimizing layouts with analog design team Floor-planning Perform physical verification (DRC,ANT,LVS,ERC, ) Development and maintenance of layout software automation capabilities Work with a team of world-class engineers who are willing to help when needed and are happy to receive help when offered What You ll Need Bachelors in Electrical/Computer Engineering, EngSci, or equivalent Familiarity with high-speed analog layout, electronics and CMOS transistors Bonus points if you have worked in recent FinFet technologies (7nm, 5nm, etc) Minimum of 2 years of custom layout experience The position is located in Vancouver 5+ years of experience is preferred About You Excellent communication skills Able to listen to and appreciate ideas and opinions that differ from yours Extremely detail oriented Superb analytical and problem-solving skills Drives for consistency Takes personal pride in high standard of outputs Self-motivated and self-managing

The Opportunity Were looking for the Wavemakers of tomorrow. Custom Layout / High-Speed Analog Layout Engineer Alphawave IP builds industry-leading wired connectivity solutions that enable data to travel faster, more reliably, and with higher performance at lower power. Our technology is embedded in leading-edge semiconductors built to power global network and computer systems. It is an essential part of the core infrastructure enabling next generation services in data centers, artificial intelligence, 5G wireless infrastructure, data networking, autonomous vehicles, and solid-state storage. The Opportunity The Alphawave IP team combines technologists from different disciplines who come together with a shared passion for electronics, software, and communication technology. We look for individuals with a deep desire to build great products and we value collaboration, curiosity, and a commitment to solving hard problems. The Alphawave Custom Layout team is composed of a group of highly technical, innovative, and passionate engineers, collaborating to develop the analog layouts and architectures for our world class high-speed SerDes IP s. What You ll Do Custom analog layout design for industry leading high speed Serdes architectures Working in leading edge semiconductor nodes and cad tools including latest 3nm node Detailed collaboration in optimizing layouts with analog design team Floor-planning Perform physical verification (DRC, ANT, LVS, ERC, ) Development and maintenance of layout software automation capabilities Work with a team of world-class engineers who are willing to help when needed and are happy to receive help when offered What You ll Need Bachelors in Electrical/Computer Engineering, EngSci, or equivalent Familiarity with high-speed analog layout, electronics and CMOS transistors Bonus points if you have worked in recent FinFet technologies (7nm, 5nm, etc) Minimum of 2 years of custom layout experience The position is located in Vancouver 5+ years of experience is preferred About You Excellent communication skills Able to listen to and appreciate ideas and opinions that differ from yours Extremely detail oriented Superb analytical and problem-solving skills Drives for consistency Takes personal pride in high standard of outputs Self-motivated and self-managing Diversity & Inclusivity Alphawave IP is based out of one of the most diverse countries in the world. This includes differences related to race, ethnicity, national origin, gender, gender expression and presentation, sexual orientation, religion, age, ability and socioeconomic status. To us, diversity is one our strongest assets to our organization. We commit ourselves to promoting the recognition and appreciation of our diverse and rich culture. We believe that it is critical to our success to promote freedom of thought and opinion in a respectful environment. The decisions we make are rooted by respectfully considering each other s thoughts and opinions and by working towards a greater common goal, saving lives. Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 3,5,7,14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

Job Title: Jr. Engineer - Quality Job Purpose: Control Panel Manufacturing Role Type: Individual Contributor Preferred Professional Education: Diploma/Degree Electrical/Electronic Engineering. Job Summary: This position is responsible for the physical inspection, Documentation and non-conformity management for the control panels of renewable products. This role involved building strong relationship with CFT like Design team, Supplier, Supplier Quality and Sourcing team to improve the product quality. Roles & Responsibilities: Inspect all electrical parts as per QAP / inward checklist / BOM/Specification/ISO & DIN standard. Raise NCR for the material which is non-confirming. Check & preserve all Test reports of the major components. Witness all sub assembly electrical connection, cable tightness & cable routine. Verify in process checklist for serial, Batch numbers. Perform/Witness the functional testing for the electrical panels. Review calibration logs for testing instruments. Collaborate with design team for the solutions and improvements. Communications with supplier for the supplier issue resolutions. Root cause analysis for the internal defects. Continual improvements. Work experience: 2 to 5 years of experience in the quality department of control panel manufacturing Hands-on experience in quality inspection and testing of control panels for renewable products. Quality Experience in control panel for renewable products/industry is preferable. Skills Required: Managing Complexity Taking Ownership Living Customer Orientation Enabling Collaboration Promoting personal growth Driving change Must be very detailed oriented and strive to achieve high quality results. Ability to multitask, prioritize, organize and adhere to written procedures. Professionalism, a positive attitude and willingness to work as a team. Must be able to simultaneously handle the demands of internal and external customers. Good communication skill.

Your role will be to meet customers/prospects and identify qualify the opportunities, work out agreeable, equally importantly achievable, evaluation criteria, run through the evaluation and convert the opportunities into business and help customers to deploy the tool and get it running into production at the earliest. It requires a very good understanding of customer flow and a good analytical ability to resolve issues impacting production schedule. Hands-on knowledge of Advance Node layout and design rules would be a plus. The role demands a close interaction with RD and Product Engineering team for implementation of new features and bug fixes. As the job requires an extensive interaction with customers for issue resolution and identifying opportunities to proliferate Cadence technologies, at the same time a closer interaction with RD and other stakeholders, it demands an excellent customer and communication skills, and the leadership qualities. This position requires solid understanding of IC design technology and foundry process/methodology in analog layouts. It is essential to have a very good understanding of analog layout design fundamentals, advance node virtuoso techfile constraints and in-depth knowledge and hands-on experience on writing skill scripts to perform various layout automation tasks. The candidate should have knowledge of complete analog back-end flow from top level floorplanning down to complex block level layouts, physical verification, extraction, EMIR analysis etc, with proficiency in Cadence layout tools specifically Virtuoso with advance node exposure. Prior Design experience using Cadence CustomIC Physical Design tools (Virtuoso) and flows including chip integration and signoff is an added advantage. - B. Tech or equivalent with 3 to 5 years of relevant experience.

We are seeking a highly skilled experienced PDN PV expert to join our Flows Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope of Responsibilities: As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define PDN PV flow methodology to meet SoC IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC designs You will work with EDA Vendors to proactively review latest tools and flows offerings in PDN PV domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. You will be an actor of change for deploying new tools methodologies across the organization Qualifications Bachelor or Master or Ph. D. in Electronics Engineering and specialization in VLSI domain 10-15 years of hands-on experience in PDN (IR Drop EM analysis) PV (Physical Verification) domains Experience on PDN PV Signoff on lower tech-nodes Ability to debug PV issues (LVS, DRC, ERC, ANTENNA, ESDLUP etc) IR-EM-Power issues independently Ability to drive PDN PV methodology automation Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can - do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

[ Location: NOIDA] Exp: 06-15Y We are seeking a highly skilled experienced PDN PV expert to join our Flows Methodologies Team. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope of Responsibilities: As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define PDN PV flow methodology to meet SoC IP level objectives on low geometry nodes (3/5/16nm) Your scope of work will cover tools and flows definition, requirement management for SoC designs You will work with EDA Vendors to proactively review latest tools and flows offerings in PDN PV domains. Evaluate latest offerings and benchmark with organization used tools, flows, and methodologies. You will be an actor of change for deploying new tools methodologies across the organization Qualifications Bachelor or Master or Ph. D. in Electronics Engineering and specialization in VLSI domain 6-10, 10-15 years of hands-on experience in PDN (IR Drop EM analysis) PV (Physical Verification) domains Experience on PDN PV Signoff on lower tech-nodes Ability to debug PV issues (LVS, DRC, ERC, ANTENNA, ESDLUP etc) IR-EM-Power issues independently Ability to drive PDN PV methodology automation Strong scripting skills for Automation and Flow development using PERL/TCL/Python. Can - do attitude, openness to new environment, people and culture Strong communication skills (written and verbal), problem solving, attention to detail, commitment to task, and quality focus Ability to work independently and as part of a team Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

We are looking for an experienced Physical Design Lead with expertise in Netlist2GDSII implementation , including floor planning , power grid design , CTS , STA , and physical verification . The ideal candidate will have proficiency in Cadence and Synopsys tools and experience with 16nm and below technologies , along with a strong background in SoC integration and low-power/high-speed designs . Leadership in managing teams, handling complex designs, and proficiency in Tcl/Tk/Perl programming is essential, along with excellent communication and customer interaction. Roles & Responsibilities: You should have 10+ years of hands-on experience with Netlist2GDSII implementation , including key processes such as floor planning , power grid design , placement , clock tree synthesis (CTS) , routing , static timing analysis (STA) , power integrity analysis , physical verification , and chip finishing . Expertise in physical design methodologies with experience working on sub-micron technologies (16nm and below). Proficiency with PnR tools from Cadence and Synopsys ( Innovus , ICC2 ). Strong background in Static Timing Analysis (PrimeTime SI) , EM/IR drop analysis (PT-PX, Redhawk) , and physical verification (Calibre) . Practical knowledge in applying methodologies and physical design tools, with experience in flow automation and process improvements . Hands-on experience in SoC integration , low-power and high-speed designs , and advanced physical verification techniques . Proven success in handling designs with >5M instance count and 1.5GHz frequency . Expertise in programming (Tcl/Tk/Perl) to automate design processes and improve efficiency. Excellent customer interaction , communication , and teamwork skills, ensuring smooth collaboration with internal teams and clients.

Job TitleAI/ML Engineer - Time Series Forecasting & Clustering LocationBangalore Experience2+ Years Job TypeFull-Time Mandatory Skills: AI/ML Engineer with Time Series Forecasting & Clustering experience Responsibilities in Brief: Time Series Forecasting Build models to predict trends from time series data. Clustering Develop algorithms to group and analyze data segments. Data Insights Analyze data to enhance model performance. Team Collaboration Work with teams to integrate models into products. Stay Updated Apply the latest AI techniques to improve solutions. Qualifications: Education Bachelor s/Master s in Computer Science or related field. Experience Hands-on experience with time series forecasting and clustering. Skills Proficient in Python, R, and relevant ML tools Perks & Benefits: Health and WellnessHealthcare policy covering your family and parents. FoodEnjoy scrumptious buffet lunch at the office every day. Professional DevelopmentLearn and propel your career. We provide workshops, funded online courses and other learning opportunities based on individual needs. Rewards and RecognitionsRecognition and rewards programs in place to celebrate your achievements and contributions. Why join Relanto Health & FamilyComprehensive benefits for you and your loved ones, ensuring well-being. Growth MindsetContinuous learning opportunities to stay ahead in your field. Dynamic & InclusiveVibrant culture fostering collaboration, creativity, and belonging. Career LadderInternal promotions and clear path for advancement. Recognition & RewardsCelebrate your achievements and contributions. Work-Life HarmonyFlexible arrangements to balance your commitments. To find out more about us, head over to our Website and LinkedIn

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. As a Physical Design Engineer, you will: Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure at the block and Sub System level. Drive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off. Work closely with third party design and fabrication services to deliver quality first pass silicon that meets all performance, power and area goals. Drive and Develop Physical Design Tool features, Flow automations and Methodology enhancements in order to achieve PPA goals, low power requirements. Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. Teams BS in EE/CS Minimum 5years of experience in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO Scripting experience with Tcl, Perl or Python and ability to drive physical design flow automation. MS or PhD degree in Computer Engineering/Electrical Engineering or related field Excellent communication and analytical skills Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO Minimum 7years of experience in integrating IP and ability to specify and drive IP requirements in the physical domain Thorough knowledge of device physics, custom/semi-custom implementation techniques Experience solving physical design challenges across various technologies such as CPU, DDR, PCIe, fabrics etc. Experience in extraction of design parameters, QOR metrics, and analyzing trends Experience with DFT & DFM flows Ability to provide mentorship, guidance to junior engineers and be a very effective team player

ROLE DESCRIPTION Expectations from the Role / Job: - END RESULTSMAJOR ACTIVITIES Spares Shipment In- warding and Storage:- -Verification of spares shipments w.r.t. invoice/ challan. - Shortage /Excess reporting to all the stake holders (If any) - Timely inward of spares shipment in SAP - Storage of Spares in prescribed Storage bins and racks. - Ensuring timely receipt updating of defectives from ASCs and handing over to warehouse technician for further process. - Maintaining Excel Storage location for convenience of pickup of spares against Orders. Physical Stock Verification:- - Spare Parts Physical Stock verification at warehouse. - Arranging porting the entries of spares stocks in SAP. ASC Spares Order and STO dispatch Management:- - Generation of invoices in SAP and checking - Arrangement of Spares picking and packing. - Arranging cartons for dispatch of spares to location/ ASCs. - Arranging dispatch of Spares shipment to ASC through Courier. - Creation of STO & deliveries in SAP and despatch to other WHs. - Preparation of Despatch MIS and sharing to SIC & ASCs on daily basis ASC defective / Fresh Stock settlement:- - Settlement of ASC Defective spares in SAP & sharing the details to ASC - Reconciliation of ASC consignment stock in SAP Defective stock clearance:- - Vendor Return to be done on monthly basis as per Product warranty tracker - Disposal Stock activity to be done on monthly basis Warehouse Hygiene:- - Timely Warehouse cleaning activity to be performed. - Proper stock keeping in Bins/racks / pallets - Proper excel tracking of SKUs bin location Skills & Knowledge - Educational Qualifications: Graduate / Post Graduate - Relevant Experience : 5 Yr.+ - Personal Characteristics & Behaviours

Role: Executive Experience: 3 to 4 years of finance & accounts experience Qualification: CA / CA (Inter) / ICWA / ICWA (Inter) / MBA (Finance) / B. Com. Department: Business Process Audit Industry: Any industry - working in finance & accounts Job Location: Bangalore Field work required for this role : 15-20 days in a month (PAN India) Job Description: Discounted Sale Audit Physical verification of claims Physical Audit of Stockiest Report preparation Debit Note Calculation Settlement of Debit note with Stockiest Closely work with Business for suspicious order monitoring and identify stockiest / parties with potential wrong practices Connect with parties and verify the suspicious orders Monitoring orders trend of Distributors, Hospitals and Doctors Analysis of deviations - Business limit vs Bill value Physical and digital audit of the orders Visit Distributors across country for physical audit

Sr. Executive AM - Stores and Purchase: About Company: CMR Green Technologies Limited CMR Group is India's largestproducer of Aluminium and zinc die-casting alloys. With 13 state-of-the-artmanufacturing plants across the country, CMR has become the preferred supplierfor many of Indias largest automotive industry leaders. Since its inception in2006, CMR has consistently outpaced competition by focusing on deliveringsuperior value to its stakeholders. This value is driven by a strong commitmentto technical advancements, quality enhancement, sustainability, andpeople-centric practices. We believe in an " Employee First " philosophy, ensuring that our people are at the core of our success. Our dedication tofostering an enriching work environment is reflected in our recognition asthe 'Most Preferred Place for Women to Work' and as one ofthe Top 25 Mid-Sized Indias Best Workplaces in Manufacturing for 2025 by GreatPlace to Work. As CMRcontinues to chart its growth trajectory, we remain committed to innovation andexcellence. We are always looking for enthusiastic and dynamic individuals tojoin our team and contribute to our continued success. Position: FLO - Stores and Purchase Job Band - A Designation: Sr. Executive/AM - Stores andPurchase No. of Posts: One (1) Department: Stores and Purchase Reporting to: Area Head- Storeand Purchase Qualification: Essential Graduate /Professional degree / Diploma from reputed recognized institute (FullTime). Desired - Degree / Diploma / MBA In MaterialManagement Experience: Essential: Around 3 to 5 years ofexperience in Stores and Purchase in any Manufacturing setup. Desired: Experience Advance stores ManagementPractices would be preferable. Job Profile: Primary Responsibilities Supporting to implement & sustain processes, policies and Standard Operating Procedures for purchase & stores in plants. Experience in Indirect Purchase. Collecting Material requirement & floating enquiry, making CS for approval. Placing Purchase order after approval & sending vendorto dispatch material. Follow up material until reach site. Review material requirements & inward shortages ofmaterials and ensure action steps for fulfilment of shortages. Consumables stored as per the applicable storage guidelinespertaining to temperature, volume, hazardous material, etc. Timely availability of stores items, spares & rawmaterials, by efficiently coordinating & planning with the purchase team. Accuracy of inventory with respect to reconciliation betweenphysical availability of material and system availability. Drive adherence to physical verification/ cycle counting ofmaterial timelines and processes. Utilization of storage space by planning inventory volumes & optimum store space utilization & ensure adherence to various normsand safety conditions in the process. Ensure systematic documentation & forwarding of reportsto Lead Purchase & Stores and issue of materials to customers as per therequirement and record maintenance for the same. Required Competencies: Effective communication Teamwork Knowledge sharing and learning Planning and organization Execution excellence Results orientation General: Candidate should not be a frequent job changer. CTC range 3LPA to 6.50 LPA. Age- 25-30 years Notice Period- Joining period Max 30 Days. We can buy noticeperiod, if required. Location: Sriperumbudur A4 & 5, SIPCOT IndustrialPark, Pillaipakkam, Sriperumbudur, District Kancheepuram, Tamil Nadu- 602105

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Software Engineer Grade : T3 Experience: 4-6 Years Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary & Technical Skills required: We are seeking a highly motivated software engineer to be a part of the Pegasus Physical Verification System Product Development Group. The role involves designing, development, profiling, optimizing, and supporting application software for Design Rule Checking (DRC), Layout Versus Schematic (LVS), Advanced FILL, and Programmable Electrical Rule Checking (PERC). The job responsibilities include development of data analysis and debugging tools for performance analysis, research and development of data driven optimizations of geometric and topological operations for physical verification applications, troubleshooting and debugging physical verification software on large complex databases, collaborative development and testing of advanced functionality with multiple geographically distributed teams. The role requires a strong programming (C++ and/or python) and software engineering skills, analytical and problem solving skills, an ability and interest to learn and adapt to changing requirements and technologies, and in possession of strong interpersonal and communication skills, as well as a collaborative and growth mindset. Minimum Background Requirements: Knowledge of algorithms and Software Engineering Skills. Good to have C++/python Experience with UNIX and/or LINUX platforms Desired Background: Experience in software development, preferably in EDA. Experience in Physical Verification (DRC, LVS, FILL, PERC) Strong understanding of advanced semiconductor process technologies. Experience and Technical Skills required: Educational Qualification: Bachelor s degree in Electrical Engineering with Microelectronics/VLSI Design or related discipline from an accredited institution or equivalent We re doing work that matters. Help us solve what others can t.

Name of the Company Tatva Chintan Pharma Chem limited Position Officer/Sr.Officer -Store Role Purpose To maintain inventories, ordering new items, placing products on shelves, pulling our expired items, and keeping records of transferred merchandise. Role Reports to Manager -Store Qualification Any Graduation + Material Management Years of experience 3-6 Years 1. To maintain Inward/outward register of any type of materials. 2. To maintain activities of loading/unloading of materials with physical verification of weight and maintain register. 3. To maintain daily calibration of weight balance and maintain register. 4. To issue material to plant as IT issue.(RM/WIP/PM Etc.) 5. To maintain dispensing log book as per the SOP in RM issuance. 6. To clean area and maintain temperature of humidity with register. 7. To arrange local tempo and maintain register of charges. 8. To maintain dispensing labels on drum of batch issuance 9. To go to outside of factory for weight bridge of material. 10. To shifting of materials as per instruction. 11. To prepare GIM and send to QC 12. To prepare Returnable Gate pass of materials & maintain register. 13. To prepare RMTC label & affix on drum. 14. To prepare statement & maintain register of drums. II | P a g e 15. To stock taking on monthly basis for all material. 16. Godown Related all works i.e prepare Annexure B A Physical stock taking etc. 17. For handling and controlling hazardous materials and hazardous waste. Outstanding interpersonal and communication abilities. Strong multitasking and organizing skills. Ability to resolve conflicts and address problems. The capacity to operate both individually and jointly. Precision and meticulousness in the administration of information. Ability to adjust and be flexible in the face of shifting conditions or priorities.

RPG Group JOB DUTIES Job Summary: Responsible for planning, implementation and evaluation of the logistics of the transmission line Key Accountabilities Duty Statements Planning and Implementation: Lodge police complain and insurance claim on the event of any loss / theft / damage of any store material during transit / erection and inform to PM Maintain a cost book for daily expenses made at store Prepare Monthly Stock Statement, Monthly Material reports and Consolidated Statement and also update stock ledger and maintain fixed asset register Responsible for physical and computerized reconciliation of stock Materials Issue to sub contractors on debit able basis with proper authorization and as per work order terms Prepare debit note against rejection, shortage and damage material at site Responsible for arrangement of Transport for material shifting and coordinate other store for material shifting receiving & shortage Prepare Goods Receipt Note & Follow up the shortage materials by sending reminders to H.O. & as well as to supplier Maintain and update information in ERP for each movement Organize proper identification, location and display of material stacking Ensure timely storage of materials at site with right material, right quantity, right quality, right place, at right time Transferring Excess material through Stock Transfer Note Co-ordination: Liaise with project manager & coordinator and purchase department at HO for update on dispatch instruction and feed this information to Central store Supervise routine work and coordinate with HO Co-ordinate with account department for certifying all vendor bills Regular physical verification of stock and report to Head Office

Long Description Annual maintenance contract preparation and preventive maintenance of QC and IPQA instrument as per approved procedure. Breakdown handling of QC and IPQA instrument as per approved procedure. Upkeep the records of preventive maintenance and breakdown in SAP. Qualification of new instruments and SOP preparation. To participate in failure investigation related to malfunctions. To impart training to the analysts for instruments maintenance and troubleshooting. Co-ordination with vendor service engineer of service /breakdown related activities. To maintain GMP in QC laboratory, Real time documentation. Computer system validation of laboratory instruments. Execution and implementation of quality system in laboratory. Taking part in internal calibration, out-side calibration and reviewing calibration data. Taking part in instrument cleaning maintain & Maintenance of all laboratories indents. QAMS, Caliber-e-log related activities SAP Bill & invoice clearance PO & PR related activity software handling EDMS ,SAP, caliber E log, QAMS, LIMS. etc. Competencies Innovation & Creativity Result Orientation Collaboration Customer Centricity Developing Talent Stakeholder Management Strategic Agility Process Excellence Education Graduation in Mechanical Engineering Work Experience 7 to 8 Years of experience in Quality Control as Instrument Engineer

Ensure proper inventory control through SAP system Maintain stock accuracy and conduct regular cycle counts and physical verification Implement FIFO/LIFO methods and ensure proper material traceability Maintain records of GRN and stock registers Perks and benefits Transportation Canteen Accommodation