1027 Physical Verification Jobs - Page 13

Role Overview: Job Title : PNR Lead Experience : 8+ Years Work location : Bangalore Job Description: Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the de...

Job Description: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Your role will require collaboration with cross-functional teams to develop solutions and meet performance requirements. Key Responsibilities: - Demonstrating good knowledge of CMOS technology and physical design concepts such as flooplanning, place and route, clock tree synthesis (CTS), physical verification, and static timing analysis (STA). - Taking responsibility for developing CAD tool/flow solutions w...

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and Twitter (X). Person should have complete end-end knowledge of the Netlist- Gds Tapeout methodo...

Role Overview: As a Virtuoso Layout Engineer at Cadence, your main responsibility will be to engage with customers and prospects, assess and validate opportunities, define feasible evaluation criteria, convert prospects into business deals, and support customers in implementing the tool for their production needs. Your expertise in understanding customer workflows and analytical capabilities will play a vital role in addressing issues that impact production timelines. Having hands-on knowledge of Advance Node layout and design rules will be advantageous for this role. Key Responsibilities: - Communicate with customers to resolve issues and identify possibilities to showcase Cadence technolog...

Key Responsibilities: Perform physical verification at the SoC, core, and block levels, including DRC, LVS, ERC, ESD, DFM, and tapeout tasks. Address complex physical design challenges related to sign-off and ensure timely resolution. Maintain deep understanding of physical verification workflows and methodologies across RTL to GDS2. Collaborate with Place-and-Route (PNR) teams to support verification sign-offs at various stages. Troubleshoot and resolve LVS issues, particularly for complex analog-mixed signal IP integrations. Support verification of full-chip components including I/O rings, corner cells, seal rings, RDL routing, and bumps. Contribute to the development of sign-off methodolo...

Responsibilities: Work as part of the Design Enablement team, closely collaborating with SoC cross-functional teams Define and develop PDN and PV flows and methodologies for low geometry nodes (3nm, 5nm, 16nm) Manage requirements and define tools and flows needed for SoC-level implementation Collaborate with EDA vendors to evaluate and benchmark latest PDN & PV tools and methodologies Lead deployment and adoption of new tools, flows, and methodologies across the organization Act as a change agent in introducing innovative flow improvements and process standardization

As a Senior Layout Engineer at SILCOSYS Solutions, you will play a crucial role in designing and verifying analog circuit layouts. You will collaborate with circuit design teams, perform physical verification, and ensure compliance with industry standards. Your day-to-day tasks will involve layout design of analog circuits, circuit design collaborations, conducting design reviews, and resolving layout-related issues. Key Responsibilities - Design and verify analog circuit layouts - Collaborate with circuit design teams - Perform physical verification tasks - Ensure compliance with industry standards - Conduct design reviews - Resolve layout-related issues Qualifications - Experience in Layou...

As a Physical Design Engineer, you will be responsible for the physical design of ASICs. This includes tasks such as floorplanning, clock tree synthesis, placement, routing, timing closure, and physical verification. Your contributions will be crucial to the successful tape out cycles of multiple chips, ensuring the efficiency of the PD life cycle and ECO life cycle. Your expertise in clock-tree synthesis and power-aware PD flows, such as ADM, P&R, will be essential for the project's success. Additionally, your familiarity with PD-STA, timing constraints, and multi-mode, multi-corner timing closure will play a key role in achieving project milestones. **Qualifications Required:** - 3+ years ...

Role Overview: As a Store Assistant/Keeper at our office located in Rabale, Navi Mumbai, your primary responsibility will be to stock materials received from vendors properly to ensure easy access, identification, verification, and handling. You will play a crucial role in maintaining the stock by using appropriate methods of care and preservation to prevent damage and loss. Periodical physical verification of stock, smooth issuance of materials to internal departments, and accurate accounting of received and issued materials are key aspects of your role. It is essential to maintain receipts, records, and withdrawals of stock, provide necessary documents with outward materials, and ensure th...

Job Description Main Tasks Physical verification of Gold Packets, Cash including Vault Cash and Foreign Currency as to its correctness with the system records. Checking of ornaments as to its quantity, weight, quality and purity taken for pledge during the current gold inspection period. Checking of greater than 5 months gold packets as to its quantity, weight, quality and purity for which gold inspections were done earlier. Verification of Gold Loan pledge/release documents and reporting of anomalies if any observed. Verifying whether the ornaments pledged under all schemes are solid ornaments and LP/SP ornaments are not accepted for pledge under any schemes. Verification and reporting of a...

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shi...

Introduction: This position is for IO Design Engineer who will own End-to-End development of IO IPs. The successful candidate needs to have an exceptional background in CMOS design, End-to-end Analog/IO IP development experience, and needs to be a team player with a solution-oriented approach. Essential Responsibilities: Responsible for the development and delivery of IO IPs (GPIO, LVDS, SSTL, HSTL, MIPI, etc) in multiple technology nodes and achieving corresponding PPA indicators Responsible for collaborating to defining IO IP architecture design and circuit design, simulation verification and reliability assurance Collaborate in the design and implementation of test chips, packaging design...

Roles and Responsibilities Manage daily store operations, including inventory control, material receipt, and stock taking. Ensure accurate GRN (Goods Received Note) and MRN (Material Reject Note) processing for all materials received or rejected. Conduct physical verification of stored items to maintain accuracy in inventory records. Implement FIFO (First-In-First-Out) method for storing and issuing materials. Perform regular stores maintenance tasks such as cleanliness, organization, and upkeep of the storage area.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER (AECG ASIC PD ENGINEER) The Role The position will involve w...

Role: PD Lead Experience: 7+yrs Location: Bangalore Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the design (floor planning, placement, CTS, routing, ph...

Preferred candidate profile We are looking for a proactive and detail-oriented Warehouse In-Charge to oversee daily warehouse operations for our food production unit. The candidate will be responsible for maintaining accurate stock records, ensuring timely dispatches, coordinating with vendors and logistics partners, and ensuring compliance with food safety and quality standards. Key responsibilities: 1. Inventory & Stock Management Conduct daily stock audits including opening stock, consumption, closing stock, and variance reconciliation. Identify and record stock variances (Actual vs. Formula) and take corrective actions to minimize wastage. Maintain Reorder Levels (ROL) for all raw materi...

Who we are Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz (http://www-vlsi.stanford.edu/horowitz/) and Prof. Christos Kozyrakis (http://csl.stanford.edu/christos/). What we do Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must. Kinara solutions embed high-performance AI into edge devi...

Title: Physical Design Lead (PnR, STA) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Job Summary The individual will reports into the Design Methodology group and will be part of a team that is responsible for the creation of Design Methodology solutions for a wide variety of ...

Skills requried: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes. Should have experience in Analog and Mixed Signal Design Should have experience in handling >5M instance count , 1.5GHz frequency designs. Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency. Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2) Strong experience on Static T...

Job Description In your new role you will: Contribute to the implementation of highly complex automotive SoC designs in a multi-site organization covering all aspects of Physical Design. Work independently in different phases of the RTL2GDS flow: With focus on (one or many) Synthesis, Constraints and equivalence check, Generation of Floorplans, Placement, Clock Trees, Routing and Power Distribution Network for efficient Timing Closure with Signal Integrity and Physical Sign off including Power Integrity Work with industry standard tools for physical design and signoff with good understanding of scripting languages (shell, perl, tcl) and Make flow. Focus on PPA, define the Partition shapes, p...

Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Job Description In your new role you will: Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Design Application Engineering (DAE) will be responsible for supporting project teams using Infineon Design System (Flows, Design Package & Design assistance). You will be the first point o...

Finalization of accounts for monthly closing and audit purposes ,Purchase:Checking of quotations received from the purchase team and judiciously verifying the genuineness of the quotations Checking of vendor bills with respect to documentation and statutory compliances Ensure timely payment to vendors and timely payment of payroll Payments and petty cash":Control over petty cash by timely recording of the receipts, payments and verifying the closing balance of cash with book balance on daily basis Timely payment to vendors after checking the documentation and aspects of TDS and other statutory compliances ,Banking:Co-ordination with bankers for payments, receipts, bank charges and other bank...

Implementation with emphasis on Physical Verification & project finishing/tapeout activities Own and execute Physical Verification flow with in-depth experience in analysing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues ( Calibre/ICV ) Own and execute PV activities at the block and sub-system levels Work closely with PD team in addressing PV issues and provide solutions Contribute to SoC-level PV sign-off checks What Youll Need: 10+ years of Physical verification experience Experience with physical verification checks - DRC, LVS, Antenna, ERC, PERC, ESD etc. using Calibre/ICV Excellent debugging skills and experience with fixing base DRC, metal DRC, especially w.r.t. ...

Implementation with emphasis on Physical Verification & project finishing/tapeout activities Own and execute Physical Verification flow with in-depth experience in analysing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues ( Calibre/ICV ) Own and execute PV activities at the block and sub-system levels Work closely with PD team in addressing PV issues and provide solutions Contribute to SoC-level PV sign-off checks What Youll Need: 3+ years of Physical verification experience Experience with physical verification checks - DRC, LVS, Antenna, ERC, PERC, ESD etc. using Calibre/ICV Excellent debugging skills and experience with fixing base DRC, metal DRC, especially w.r.t. d...

Looking for a Senior VLSI Engineer (PV) with 10+ years of experience in IC design front-to-backend flow, strong in Physical Verification, C-shell scripting, Tcl/Perl, and Linux/UNIX environments. Location: Bangalore. Required Candidate profile Experienced VLSI Physical Verification professional skilled in C-shell,Tcl, and Perl scripting with deep knowledge of IC design flow& UNIX/Linux environments. Proven expertise in semiconductor design.