812 Physical Verification Jobs - Page 12

Requisition ID: R-39104 Role Title: Logistic Executive Work Level: 1B Work Location: Etah beverages Factory, HUL Main Role: The Executive is responsible for export logistics operation, Ties up with customer for scheduling of exports with ensuring all exports compliance with Local Government requirement such as Excise, customs etc. He liaises with Production & Planning team to schedule hassle free export and full fill customer order in time. Execute continuous improvement projects through the application of harmonized logistics processes and systems followed across UIEL & rest of the sites of Instant Tea Powder. Implement process improvement through operational scorecards and get timely feedb...

materials, tools Engineering item Engineering equipment Inventory Management Material Handling Stock Control Record Keeping Store Operations Coordination Compliance Reporting Required Candidate profile if it is manufacturing industry

Education : BTech in ECE/EEE or MTech VLSI No. of positions : 5 Desired Skills: Minimum 3+ year of experience Should have block/SOC level netlist-gds2 experience. Expertise in Floor planning, Power planning, CTS. Should be capable of handling block-level timing closure. Good scripting skills (TCL/Perl/Shell). Experience on low power implementation techniques is preferred. Synopsys/Cadence tool experience is preferred. Should be a team player and perform lead role where ever required. Good communication analytical skills.

Physical Implementation activities for Sub systems include Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. You should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Your expertise should include timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. You should be well-versed with Block level PnR convergence using Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. A good understanding of clocking architecture is essential. Collaboration with design, DFT, and PNR tea...

This position is for an Analog Layout Engineer role who should have the below required knowledge and skills - - Should have good understanding of semiconductor / Analog Layout & Physical verification basics. - Good hands-on Block level scratch Layout work, floor plan, placement, routing - Hands on in 28nm/22nm/ 14nm/ 7nm/ 5nm is desirable - Should understand Analog layout concepts on BGR / LDO/ OPAMP/ ADC/ DAC etc - Hands on Layout exposure to matching techniques like Inter-digitization and common centroid on current mirrors and differential pairs. - Should have good understanding of full custom layout implementation and Layout dependent effects - Good matching and other analog layout relate...

Physical Design Lead, Manager Job Description The Physical Design Manager leads and mentors teams responsible for designing and delivering customer-specific silicon solutions based on detailed requirements. This role drives the creation of custom integrated circuits (ICs) and oversees building a solid re-use methodology, enabling fast turnaround through physical design flows and ensuring project efficiency, quality, and innovation. Key Responsibilities Manage and mentor a team of physical design engineers, overseeing project schedules, resource allocation, and team performance. Lead all phases of the physical design process, including synthesis, floor planning, placement, clock tree synthesi...

You will be responsible for the further development of concepts and methods for the EDA design environments with focus on analog / mixed signal CAD flows. Expert level proficiency in one or more of the programming/scripting languages SKILL, Python, Unix, Perl and TCL. Expertise in Virtuoso suite of tools and Analog Design environment (finesim/PrimeSim) Solid understanding of Calibre Physical Verification decks(SVRF) and ICV LVS decks with hands-n experience in integrating various PV flows in CAD environment. Solid experience in Layout Automation and Utilities development in Cadence SKILL/SKILL++. Development and validation of PV tools and flows like parasitic extraction, EMIR drop and substr...

Position Overview: We are looking for a highly skilled and experienced individual for SoC PD lead position for driving SoC implementation efforts from RTL to GDSII. This role is pivotal within our talented team of engineers, ensuring that we meet our GDS release timelines, PPA requirements, and all sign-off criteria for our complex semiconductor designs. This role demands a profound technical understanding of the entire implementation cycle, from start to finish, as well as exceptional leadership skills. The successful candidate will work with various functional teams and must possess a strategic vision to drive continuous improvement in our methodologies and processes. Key Responsibilities:...

Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, sc...

Hiring Audit Associates – Commerce Students Only Key Role: Mandatory travel to multiple store locations of multinational companies Own bike required (petrol reimbursed) Work on Stock, Quality & Inspection Audits Perks and benefits Petrol reimbursed

We are looking for a highly skilled and experienced PDN (IR Drop & EM analysis) & PV (Physical Verification) expert to be a part of our Flows & Methodologies Team. This role necessitates strong analytical capabilities, meticulous attention to detail, and effective collaboration with cross-functional teams. Proficiency in EDA tools along with a comprehensive understanding of digital design principles are crucial for excelling in this position. The position is based in Noida and follows a hybrid model with 3 days in the office. The ideal candidate should have 6 to 15 years of relevant experience in the field. Key Responsibilities & Skills: - Collaborate closely with SoC cross-functional teams ...

As a Senior ASIC Physical Design Engineer at Synopsys, you will play a crucial role in shaping the future of the semiconductor industry by driving innovations in IC design and physical implementation. Your expertise in high-performance digital design, low-power design, and high-speed clock design will be instrumental in developing cutting-edge solutions for creating high-performance silicon chips. You will collaborate with cross-functional teams to streamline the physical design process, enhance product offerings, and exceed customer expectations. Your responsibilities will include floor planning, developing timing constraints, physical synthesis, clock tree optimization, routing and extract...

You are a Senior Principal Analog Layout Engineer at OnSemi, responsible for developing high-quality layout for complex AMS IP blocks including voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, and drivers. You will lead a team of 4-6 engineers, review their work, and drive continuous quality improvements. Your responsibilities include estimating schedules, managing manpower resources, and planning layout activities to ensure timely completion. In this role, you will contribute to area estimation, optimization, floor planning, power routing, shielding, and physical verification such as DRC, ERC, LVS, and ESD. Additionally, you will support the team in taping o...

You should have a Bachelor's or Master's degree in Engineering with 3 to 5 years of experience in Physical verification at block-level and chip-level. You must have expertise in DRC, LVS DFM, Antenna, Density Fill Routines, and other Tape-out sign-off processes. Proficiency in using Synopsys ICC Tool is required, along with tape-out experience of multiple complex chips at 14 nm or below. You should be familiar with Mentor Calibre or Synopsys ICC and ICV tools and have programming skills in tcl, Perl, or C. In this role, you will be responsible for planning and addressing electrical considerations like EM, IR, Noise, etc., throughout the design process. Exposure to physical verification flow ...

As a Physical Verification Engineer at Alphawave Semi, you will play a crucial role in accelerating data communication for the digital world of tomorrow. Your responsibilities will revolve around implementing Physical Verification processes with a focus on project completion and tapeout activities. You will be tasked with owning and executing the Physical Verification flow, showcasing expertise in analyzing and resolving issues related to DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck using tools like Calibre/ICV. Collaborating closely with the PD team, you will address PV challenges and contribute to SoC-level PV sign-off checks. To excel in this role, you should bring to the table at lea...

As a Layout Design Engineer at Micron Technology's HBM Team in Hyderabad, India, you will be involved in designing layouts for intensive applications such as artificial intelligence and high-performance computing solutions like High Bandwidth Memory. You will collaborate with peer teams globally and work on multiple projects simultaneously. Your responsibilities will include designing layout for leaf cell/Stdcell or sub block, possessing a strong understanding of MOS basics, fabrication fundamentals, and Analog layout basics. You should be highly motivated, detail-oriented, and approach IC layout design with a systematic and methodical mindset. Demonstrating commitment to your assignments an...

RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification Will be closely collaborating with EDA vendors and PDK to define, implement, customize, and qualify digital design flows Uses TCL, Python, Pandas and Google APIs to create automation for flow regressions, to collect and compare flow errors, warnings and key design metrics to ensure good quality PDK release and released flow backward compatibility to PDK Use reference flows to perform cross tool and PDK PPA benchmarking Define and generate design testcases to target and measure specific aspects of GLOBALFOUNDRIES PDK and technology changes Work independently in an international...

RTL2GDS flow creation and qualification for Synthesis, Place and Route, Extraction, Timing and Physical Verification Will be closely collaborating with EDA vendors and PDK to define, implement, customize, and qualify digital design flows Uses TCL, Python, Pandas and Google APIs to create automation for flow regressions, to collect and compare flow errors, warnings and key design metrics to ensure good quality PDK release and released flow backward compatibility to PDK Use reference flows to perform cross tool and PDK PPA benchmarking Define and generate design testcases to target and measure specific aspects of GLOBALFOUNDRIES PDK and technology changes Work independently in an international...

Role & responsibilities Prepare, review, and manage commercial contracts, agreements, and documentation. Handle vendor registration, negotiations, purchase orders, and procurement activities. Manage tenders and bidding processes including preparation of tender documents, submission, and follow-up. Evaluate quotations, finalize commercial terms, and ensure cost optimization. Monitor and track purchase requisitions, deliveries, and invoice processing. Maintain vendor database and ensure timely payments in line with agreed terms. Assist in budgeting, forecasting, and financial analysis related to commercial activities. Ensure compliance with statutory, legal, and company policies. Liaise with c...

Roles & Responsibilities : Hands on experience in developing Analog Layout / IO layout design. Good exposure on FinFet layouts in lower nodes. Expertise in using the best and latest features of Cadence and Calibre DRC/LVS. Good exposure on ESD, LUP, antenna layout challenges and analysing/fixing EMIR issues. Capable of working independently and with team and getting work done. The ability to work communicate effectively with global engineering teams.Able to handleAnalog Layout Design, EDA Tools, DRC, LVS, Calibre, FinFet Secondary Skills Knowledge in Cadence, Virtuoso, Physical verification.

Wipro Limited is a leading technology services and consulting company dedicated to creating innovative solutions that cater to the most complex digital transformation requirements of clients. With a global presence spanning 65 countries and a workforce of over 230,000 employees and business partners, Wipro is committed to helping customers, colleagues, and communities thrive in an ever-evolving world. For more information, please visit www.wipro.com. As a Physical Design Lead, you will be based in Bangalore, Hyderabad, or Pune with a minimum of 8 years of experience. Your responsibilities will include handling Netlist2GDSII Implementation tasks such as Floor planning, Placement, CTS, Routing...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity t...

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your role will involve launching cutting-edge, world-class products by collaborating with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or ...

You will be responsible for Physical Implementation activities for sub systems, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. Your role will involve ensuring good exposure to PD implementation of PPA critical Cores and making the right PPA trade-off decisions. You should possess knowledge in timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. Additionally, familiarity with Block level PnR convergence using tools like Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus is essential. A good understanding of clocking architecture is required...

Qualcomm India Private Limited is seeking a skilled Hardware Engineer to join the Engineering Group. In this role, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to contribute to the development of world-class products. Collaboration with cross-functional teams will be essential to meet performance requirements and drive innovation. The ideal candidate should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with a minimum of 4 years of Hardware Engineering experience. Alternatively, a Master's degree...