Physical Verification Engineer

🔧 Job Title:

🏢 Industry:

📍 Location:

🧠 Experience:

📅 Employment Type:

Urgent Requirement

Apply only if you are available to join immediately or have a notice period of 30 days or less.

Please do not apply

Key Responsibilities:

• Own and execute

  Physical Verification flow

  across block, sub-system, and full-chip levels.
• Perform and debug checks such as

  DRC, LVS, ERC, DFM, Antenna, PERC

  , and

  ESD

  using

  Calibre

  or

  IC Validator (ICV)

  .
• Analyze and debug

  rule deck issues

  and implement solutions in collaboration with layout and integration teams.
• Execute PV closure and contribute to

  SoC-level sign-off activities

  .
• Apply

  runtime optimization techniques

  and support quality tapeouts.
• Script and automate PV flows using

  Perl, Python, Tcl, SVRF

  , and

  Unix/Linux

  shell.

Required Qualifications:

• 5+ years of hands-on experience in

  Physical Verification

  in advanced process nodes (7nm, 5nm preferred).
• Strong expertise in

  DRC, LVS, ERC, Antenna, PERC, ESD

  verification checks.
• Proven debugging and fixing experience in

  Innovus

  and/or

  Fusion Compiler

  environments.
• Deep knowledge of

  multi-patterning layers

  (double/triple patterning) and base/metal layer DRC resolution.
• Experience in

  LVS/Antenna debugging and fixes

  .
• Strong scripting capabilities in

  Tcl, Perl, Python

  , and

  Unix/Linux shell

  .
• Familiarity with

  full-chip integration and sign-off flows

  is a plus.

Urgent Requirement

Apply only if you are available to join immediately or have a notice period of 30 days or less.

Please do not apply

razia.begum@talentcorner.in

📱 WhatsApp (No Calls): +91 87904 31010