432 Physical Design Jobs

In-depth knowledge and hands-on experience on Netlist2GDSII Implementation . Must have hands-on experience on Synopsys/Cadence tools. Should have experience on PD Methodologies and submicron technology of 28nm and lower technology nodes.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We dont need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 8 - 12 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday #LI-EDA #LI-HYBRID

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 5-7 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday #LI-EDA #LI-Hybrid #DVT

Responsibilities: Promptly attend site problems arriving at customer premises in low voltage motors. Carry out overhauling of motors at customer premises. Maintain excellent relationship with the customers & Authorized Repair Center. Help in generating service business e.g. motor overhauling, AMC, spare parts, complete motor retrofitting, Motor rewinding etc. Analyze site problems & give suitable solutions to customer. In some cases, co-ordinate with HO for offering solution. How do I Qualify Diploma/Degree in Electrical engineering field with excellent knowledge of Low & Medium Voltage Motors. At least 7 Years experience in servicing of Electrical motors. Having knowledge in service business development area. Capable in identifying customer end maintenance process improvement need. Excellent communication & team-work skill. Problem solving attitude.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. About the role: We are seeking a highly motivated and detail-oriented Application Support Engineer to join our dynamic, fast paced and growth-mindset team. In this role, you will be focused on supporting the Questa verification products, specifically in Verification IP line of products. In this position, you will be working closely with the product engineering team, field application engineers and customers. As an ASE, you will be solving some of our customers complex design, testbench and environment issues in the domain of functional verification. You will also be working closely on creating knowledge-based content and providing expertise on the Questa platform. You will work with multiple customers to understand their challenges and flow and be involved in technical presentations, training, evaluation and competitive benchmarking. You will part of the larger application support engineering organization and will be interfacing regularly with the North American and PACRIM teams. Minimum Qualifications BS Electronic/Computer Engineering from an accredited institution Minimum of 2+ years of Digital Design/Verification experience Knowledge of VHDL or Verilog, or SystemVerilog RTL languages for ASIC or FPGA design Experience with ASIC or FPGA hardware design and implementation using RTL tool flows and methodologies Knowledge of Windows and Linux OS Self-motivated, flexible, self-disciplined, and comfortable in a dynamic, quick-moving environment. Strong interpersonal and communications skills with the ability to quickly establish rapport and credibility with our customers, sales, and product teams. Strong oral, and written communication, and presentation skills Excellent organizational and time management skills Preferred qualifications MS Electronic/Computer Engineering Knowledge of UVM and System Verilog for Verification Clock Domain Crossing (CDC), Static and Formal Verification- Formal Applications Working knowledge of Working knowledge of Questa-Modelsim, VCS (Synopsys), NCSim (Cadence) or Aldec simulators. Knowledge of C/C++ programming languages Demonstrated proficiency with Object-Oriented Programming experience in test bench architecture and design Knowledge of scripting languages (e.g., Shell, Tcl, Perl, Python) Knowledge of CDC, low power and formal methodologies. Location Noida/ Bangalore Why us Working at Siemens Software means flexibility - Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you'd expect from a world leader in industrial software. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Transform the Everyday #Li-EDA #LI-HYBRID

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4-7 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -12+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Job Duties: --A Server I/O logic design engineer should be able to --Work with stakeholders and others in a multidisciplinary team to define functional requirements and develop the solutions. --Develop logic (VHDL/Verilog) components and microcontroller code (C) functions. --Ensure that the components are block tested and debugged by waveform analysis, and ready to be integrated into the system product. --Provide fixes to defects identified by the verification team during the development life cycle. --Support the physical design team in closing the design under timing, power, and area constraints. --Support the lab team in characterizing the hardware in the bringup lab. Skills: Knowledge of High-speed IO or analog mixed-signal domain preferred, Prior experience in logic design, directed designer simulation testing and good communication skills (written and on the phone). Tools: VHDL, Verilog, C, Git, Linux OS, KornShell & BASH scripting Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise A minimum of 7+ years of logic design experience in high-speed I/O or analog mixed-signal domain.Demonstrated experience in logic design.Proficiency in VHDL, Verilog hardware language.Familiarity with C programming Preferred technical and professional experience Prior IBM logic design experience or High-Speed IO logic design experience

Urgent Opening for Sr Engineer- Physical Design Posted On 06th Oct 2017 11:52 AM Location Bangalore Role / Position Sr Engineer- Physical Design Experience (required) 3- 9 yrs Description : Responsible for all aspects of physical design and implementation. Responsibilities include chip floor plan, power / clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation; Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical Designs Should be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC / Encounter / Talus / Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm Should be familiar with low-power design and their impact on Back end flow (power switches / Level shifter / Isolation cell / retention cells / Back biasing / Forward biasing Send Resumes to girish.expertiz@gmail.com -->Upload Resume

Urgent Opening for Physical Design Sr Engineer / MTS / SMTS Posted On 27th Jun 2017 01:05 PM Location Bangalore / Hyderabad Role / Position Physical Design Sr Engineer Experience (required) 2-7 Years Description Designation :Physical Design Sr Engineer / MTS / SMTS Experience: 2 to 7 Years Location :Bangalore /Hyderabad : Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical DesignsShould be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm/10nm Should be familiar with low-power design and their impact on Back end flow (power switches/Level shifter/Isolation cell/retention cells/Back biasing/Forward biasing) Qualifications:B.Tech / M.Tech or equivalent from a reputed University Send Resumes to girish.expertiz@gmail.com -->Upload Resume

Job Duties: --A Server I/O logic design engineer should be able to --Work with stakeholders and others in a multidisciplinary team to define functional requirements and develop the solutions. --Develop logic (VHDL/Verilog) components and microcontroller code (C) functions. --Ensure that the components are block tested and debugged by waveform analysis, and ready to be integrated into the system product. --Provide fixes to defects identified by the verification team during the development life cycle. --Support the physical design team in closing the design under timing, power, and area constraints. --Support the lab team in characterizing the hardware in the bringup lab. Skills: Knowledge of High-speed IO or analog mixed-signal domain preferred, Prior experience in logic design, directed designer simulation testing and good communication skills (written and on the phone). Tools: VHDL, Verilog, C, Git, Linux OS, KornShell & BASH scripting Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise A minimum of 7+ years of logic design experience in high-speed I/O or analog mixed-signal domain. Demonstrated experience in logic design. Proficiency in VHDL, Verilog hardware language. Familiarity with C programming Preferred technical and professional experience Prior IBM logic design experience or High-Speed IO logic design experience

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering & Electronics & Communication Engineering ready to handle the challenging problems in future technologies and designs. We are also looking for candidates with Machine Learning/AI and/or Data Science background to lead our leading-edge algorithms and AI technology within our EDA solutions to increase our design team’s productivity and chip quality and performance. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMerCome THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Individual contributor for Gate Leve Sign off Timing team to work on ASICs or Server Timing Methodology. 3+ years of Semiconductor/VLSI experience Proven problem-solving skills and the ability to work in a team environment are a must EDA Tool/Methodology development experience Thorough understanding of Static Timing Analysis. Knowledge of other VLSI domains is a plus Excellent scripting skills - TCL/Python/Shell Preferred technical and professional experience Cadence tools, Synopsys tools, VLSI knowledge, VHDL/Verilog, computer architecture, Machine Learning/AI

Skills Ability to lead a team size of minimum of 10 members who can handle Subsystem PNR Subsystem timing closure and Subsystem physical verification Experience 10-15years Job Location Bangalore, Hyderabad, Noida, Coimbatore Job Type Full Time

Mon - Fri: 11 AM - 8 PM, Sat: 11 AM 5 PM. Are you passionate about building corporate relationships and driving impactful placements? Join our fast-growing team that's transforming education through innovation and real-world outcomes.. What You'll Do - Drive corporate outreach & onboard hiring partners. Build strong relationships with HRs & hiring managers. Match learner skills with the right job roles. Coordinate interviews & ensure smooth placement closures. Track and document outreach, feedback & hiring data. Stay updated on tech hiring trends & market needs. What We're Looking For. - 1- 3 years' experience in B2B placement, client handling, or corporate relations. Strong communication & coordination skills. Proactive mindset with ownership attitude. Familiarity with CRMs, spreadsheets & tools like Slack, Zoom.

Skills SOC Physical Design Experience 3 to 15 years Job Location Bangalore, Hyderabad, Noida, and Coimbatore. Job Description: Location: Bangalore, Hyderabad, Noida, and Coimbatore. Skills: Soc level floorplanning, partitioning, timing budget generations, power planning, SOC PnR, CTS, block integration Handling timing closure of high frequency blocks. Expertise in signoff closure Timing with SI and OCV, Power, IR and physical verification at both block and chip level. Understanding constraints and fixing techniques. Experience in physical verification Understanding SI prevention, fixing methodology and implementation. Proficient in Synopsys ICC or Cadence or Mentor Olympus and Atoptech tool set. Experience in Design Automation and UNIX system. Experience in Tcl/ PERL is a plus. Primary Skills: Able to handle Soc PNR activities , SOC timing closure and SOC physical verification Secondary Skills: Able to handle SOC Synthesis, SOC IR drop, SOC Lec, SOC CLP

Job Details: Skill: SAP BODS Location: - PAN INDIA Notice Period: Immediate Joiners Employee type : C2H/FT Job Description: 1.Open to Hire/Work from any city 2.People with Total Exp of 6 + and mandatory 4 + exp in BODS will be considered 3.Notice : 2/3 weeks will be considered not more than that 4.Knowledge & Exp on SQL and PL/SQL along with BODS is required. Should have experience in Data Migration. 5.Open to Freelancers without any complications in the future (minimum 30 hrs support). 6.Work timings : 1pm to 10pm.

Immediate Openings on SAP BW Native HANA _ Bangalore_Contract Experience: 6+ Years Skill: SAP BW Native HANA Notice Period: Immediate . Employment Type: Contract Job Description 5 to 7 years experience in both BW and HANA Good skills in SQL and ABAP Well versed in Data warehousing concepts Expertise in both BW and ECC back end object development and support Extractors , experience using various SAP & other sources, ADSOs, Composite Providers, DSOs, info cubes, Multi providers, etc. Hands on and technical concepts with focus on HANA modelling. Proficient in design & development of HANA models Calculation views, procedures, Table functions etc ABAP Experience in writing & debugging ABAP code, user exits, extractors etc Shift timings - 2 PM to 11 PM IST.

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 310 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.

We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. You have: Bachelors Degree in Electrical Engineering, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required ToolsCadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices.

5 to 7 years experience in both BW and Native HANA Good skills in SQL and ABAP Well versed in Data warehousing concepts Expertise in both BW and ECC back end object development and support Extractors , experience using various SAP & other sources, ADSOs, Composite Providers, DSOs, info cubes, Multi providers, etc. Hands on and technical conceptswith focus on HANA modelling. Proficient in design & development of HANA models Calculation views, procedures, Table functions Shift timings : 2 PM to 11 PM

Role & responsibilities A VLSI (Very Large Scale Integration) Recruiter typically focuses on finding and hiring talent with expertise in semiconductor design, integrated circuit (IC) design, and VLSI technologies. Below are some of the key roles and responsibilities for a VLSI Recruiter position: 1. Talent Acquisition Sourcing Candidates: Actively source candidates for VLSI design roles, including hardware engineers, design engineers, verification engineers, and other related positions within the semiconductor industry. Job Postings: Create detailed job descriptions, post open positions on job boards, and engage with potential candidates through professional networks like LinkedIn. Screening Resumes: Review resumes and applications to identify qualified candidates based on skills and experience relevant to VLSI design roles. Interviewing Candidates: Conduct initial screening interviews to evaluate candidates' technical skills, experience, and cultural fit. Coordinate Interviews: Schedule interviews with hiring managers, VLSI engineers, and technical teams, ensuring a smooth interview process. 2. Collaboration with Hiring Managers Understand Requirements: Work closely with hiring managers and team leads to understand the specific needs for VLSI roles and the required skill set for each position. Technical Knowledge: Gain a solid understanding of the technical requirements for VLSI design and verification positions to effectively screen candidates. 3. Candidate Relationship Management Build a Talent Pool: Maintain a network of passive candidates for future opportunities, especially for hard-to-fill roles or specialized positions. Candidate Engagement: Keep candidates engaged throughout the hiring process, providing them with feedback, updates, and insights into the company culture and the role. Negotiations: Negotiate offers with candidates, ensuring alignment on salary, benefits, and other terms of employment. Share your resume at durgabhavani.b@acesoftlabs.com

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI HVL Verification. Experience5-8 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI HVL Verification. Experience3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt