432 Physical Design Jobs - Page 18

You will get an opportunity to work on latest Synopsys implementation technologies (Machine Learning, Physical Synthesis , Multi-Source CTS, etc.) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions. Working on developing and debugging RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide an appropriate solution for customers. Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA. Coming up with a proactive understanding of customers pain point and coming up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies. This role requires you to act as customers advocate while talking to inhouse R&D and be a product brand ambassador while engaging with customers. The candidate must have good exposure to methodology changes to achieve targeted PPA metrics for complex designs. At least 2 years of experience in Physical Implementation RTL-GDS. Experience in autonomously debugging and resolving synth & PnR implementation challenges. Proficiency in Synopsys implementation tools is an advantage. The individual must be self-motivated and dedicated with strong debugging skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including the ability to interface with customers and business unit personnel are essential.

You are a passionate and detail-oriented engineer with a deep understanding of Static Timing Analysis (STA). You thrive in a collaborative environment, working closely with cross-functional teams to solve complex technical challenges. Your expertise in Synopsys PrimeTime and related technologies allows you to diagnose issues and propose innovative solutions that enhance product quality. You are self-motivated, with a proven track record of executing comprehensive validation plans and delivering high-quality results. Your exceptional debugging skills and proficiency in scripting languages like Perl, Tcl, and Python enable you to streamline processes and improve efficiency. You are committed to continuous learning and staying up-to-date with the latest industry trends and advancements. What You ll Be Doing: Execute and lead product validation of Synopsyss PrimeTime tool by understanding requirements specifications and functional specifications, customer use cases. Perform in-depth customer incoming root cause analysis to understand the product weak areas and hot spots and execute proactive testing to reduce customer incoming thereby improving product quality. Collaborate with cross-functional teams such as R&D, Product Engineering, Field and Customers, recommend improvements in implementation and validation. Use product expertise to provide technical recommendations, identify, diagnose and troubleshoot issues and propose solutions to ensure quality and readiness of the product/solution for customer deployment. Demonstrate a high level of attention to detail and accuracy in all tasks. Perform risk assessments and develop mitigation strategies to address potential product validation issues. Analyze validation data to identify trends, discrepancies and areas for improvement. Prepare detailed validation reports to present to multi-functional teams and management. The Impact You Will Have: Ensure the high quality and reliability of Synopsyss PrimeTime tool, contributing to its success in the market. Enhance customer satisfaction by proactively identifying and addressing potential issues before they impact users. Collaborate with R&D and Product Engineering teams to drive continuous improvements in product design and functionality. Provide valuable insights and recommendations that influence the development and validation of future product releases. Contribute to the overall success of Synopsys by ensuring that our tools meet the highest standards of performance and reliability. Support the deployment of cutting-edge technologies in high-performance designs, shaping the future of the semiconductor industry. What You ll Need: Deep domain knowledge in Static Timing Analysis. BSEE or equivalent and a minimum of 2 years of related experience or MSEE or equivalent and a minimum of 1 year of related experience. Experience with Synopsys PrimeTime, timing analysis, ECO flows, Extraction, power, SDC constraints, advanced OCV concepts, derates, PBA timing, distributes, hierarchical STA flows, and/or physical design closure. Exceptional debugging skills. Proficient in software and scripting skills (Perl, Tcl, Python). Detail-oriented with a focus on maintaining high standards of product quality. Who You Are: Collaborative team player with excellent communication skills. Analytical thinker with a problem-solving mindset. Proactive and self-motivated individual. Adaptable and flexible in a fast-paced environment. Strong attention to detail and accuracy.

We are seeking an experienced, initiative-taking, and high-calibre individual to join our SLM Monitors group as a Monitor IP Design, Architect. Someone who thrives in a collaborative environment and has a passion for creating innovative technology. Have a strong technical background in Custom Circuit design, System Design, methodologies and tools and is adept at working with advanced finfet / GAA process challenges. Proactive analytical person with a keen eye for detail and a dedication to delivering high-quality results. Excellent communication and people skills and can collaborate effectively with internal teams and external customers. Driven by a desire to innovate and contribute to the success of our innovative technology products. Job Descriptions Looking forward to work on conceptualizing, designing and productizing state of the art Monitor IP to be used in SLM monitors realized though ASIC design flow. Work on Architecting sensing elements for on-chip Process, Voltage, Temperature, glitch and Droop monitors for monitoring silicon biometrics. You will be the part of SLM team. Individual should have strong technical experience in full custom mixed-signal circuit design, circuit simulations, working knowledge of custom layout, and pre-post-silicon characterization. Additional responsibilities include: Development of statistical simulation methodologies. Liaising with layout team to achieve best possible design solution. End to end ownership of the designed custom cells. Deployment of new circuits into test chips and post-silicon characterization Architecting new sensors and enhancing existing ones through collaboration with other architects and stakeholders. Building and refining design flows to enhance efficiency and effectiveness. Conducting pre and post-layout simulations and characterization across various design corners. Ensuring designs meet advanced finfet / GAA reliability and aging, reliability and Automotive grade requirements Working closely with the RTL, Verification and Physical Design teams for ensuing integration and Quality. Owning the product from Spec to Silicon report. Preferred skills: Strong custom design experience - specification, circuit design description and schematics. Strong understanding of device Physics and Can work independently and debug and provide circuit solutions. Hands on experience with circuit design & simulation tools, IC design CAD packages - from any EDA vendor Strong understanding of SPICE simulator concepts and simulation methods Familiar with circuit simulation tools like PrimeSim, FineSim, HSPICE or similar Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Awareness of post-layout extraction & simulation, testing in conjunction with silicon validation Demonstrated technical expertise in the productization of advanced technologies. Job Requirements BS or MS degree in Electrical Engineering with 15+ years of relevant industry experience. Sound knowledge of custom / Standard cell design methodologies, layout tools, and physical verification. Familiarity with advanced finfet / GAA process challenges, simulation techniques and modeling.

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

• Physical Design of blocks & handle Complex block implementation. • Floorplan optimization for area, Power & Timing. • Block-level PnR & close Design to meet Timing, area & Power constraints. • Implement ECOs to fix timing, noise & EM-IR violations. Required Candidate profile * Exp in RTL Synthesis for PnR using small geometry FinFET. * Strong in Physical Design incl. physically aware Synthesis, floor-planning, PnR * Logic equivalency RTL2Synthesis & Synthesis2APR netlist.