491 Physical Design Jobs - Page 19

Are you looking for a unique opportunity to be a part of something greatWant to join a 20,000-member team that works on the technology that powers the world around usLooking for an atmosphere of trust, empowerment, respect, diversity, and communicationHow about an opportunity to own a piece of a multi-billion dollar (with a B!) global organizationWe offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: You will be working with our Design team from Hyderabad to develop STA tests. These tests are intended to catch timing violations at block level /SoC. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures at block level as well as full chip level, to develop constraints and, debug the setup, perform static timing analysis and debug Timing violations. Interact with Physical design Teams and propose fixes for the timing violations. You will work closely with design engineers, custom engineers and layout engineers to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required. Requirements/Qualifications: Perform Static Timing Analysis ASIC blocks and full chip with industry lead EDA tools like prime-time / Tempus, understand different interfaces, ASIC blocks and work on constraints and develop different STA modes at full chip level. Track post layout netlist releases spef extractions and integrate the new releases into full chip STA environment. Perform verification processes with modelling and simulation using industry standard simulators Maintain technical expertise and provide training to juniors Contribute to cross group communication to work towards standardization and group success Proactively solicit input from Standards, CAD, modelling and layout to ensure the design quality Drive innovation into the future generation with dynamic work environment Previous strong experience in STA and making timing constrains Experience in taking an industrial specification and implementing the respective IP Good understanding on timing/area/power/complexity trade-offs on complex interface design Familiar with IP level verification and strong RTL debugging capabilities Experience in frontend implementation tasks such as synthesis and logic equivalence Experience in large scale mix signal circuitry design including logic implementation/verification, timing analysis/optimization an advantage Excellent problem-solving and analytical skills A self-motivated, enthusiastic team player who enjoys working with others Good communication skills with the ability to convey complex technical concepts to other design peers in verbal and written form. Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. We are seeking a skilled and hands-on DFT Engineer (Level 5) to contribute to the Design-for-Test (DFT) implementation for SoCs. This role requires strong technical expertise in scan, MBIST, boundary scan, STA closure, and silicon readiness to support high-volume SoC products. You will work in a cross-functional team environment alongside RTL, physical design, and test engineering teams. Why This Role As an L5 DFT Engineer, you will play a critical hands-on role in defining and implementing Design-for-Test (DFT) strategies for next-generation SoCs. This role offers you the opportunity to work at the heart of silicon development, collaborating with architects, RTL designers, physical design, and test engineering teams to ensure silicon is testable, and production-ready. If youre a self-motivated engineer who thrives in technically challenging environments and is passionate about high-quality, high-coverage test solutions, this role is an ideal platform to balance of technical depth, collaboration, and impactful execution on real silicon products. Key job responsibilities Insert, and verify DFT logic and components in subsystem RTL netlists. Enhance and improve DFT implementation to achieve DFT coverage targets. Review sign-off level, timing closure using static timing analysis of DFT mode. Generate and sign off high-quality pre-silicon DFT patterns. Education: BS/BE or MS/ME in Electrical/electronic or Computer Engineering or related discipline. Experience: Minimum 5+ years in semiconductor industry as a DFT engineer Technical Expertise: Insert, and verify DFT logic and components in subsystem RTL netlists. Enhance and improve DFT implementation to achieve DFT coverage targets. Generate and sign off high-quality pre-silicon DFT patterns. Scan / ATPG: Hands-on experience in scan insertion and ATPG pattern generation for high fault coverage. Debugging RTL/Gate-level mismatches during scan simulation. Experience with IEEE 1500, 1687 (IJTAG) for core-level DFT integration. MBIST / Memory Repair: MBIST, BISR, and BIHR insertion tools and methodologies. Familiarity with shared-bus MBIST architecture is a plus. Experience in memory repair signature generation and validation. Boundary Scan & IJTAG: Working knowledge of IEEE 1149.x (Boundary Scan), and 1500, and 1687 IJTAG implementation. IJTAG ICL extraction, PDL modeling using Siemens Tessent (is a plus) or equivalent. STA / Timing Closure: Static timing analysis (STA) with DFT constraints for shift and capture paths. DFT-aware timing closure in collaboration with physical design teams. Automation & Scripting: Experience in developing automated workflows using Python, Tcl, or Perl. Reusable scripts for DFT flow integration, reporting, and analysis. Soft Skills & Collaboration: Strong communication skills; ability to collaborate with RTL, physical design, test, and PE teams. Debug / Post-Silicon: Post-silicon DFT pattern validation and silicon debug. Collaboration with ATE and Product Engineering teams for bring-up and correlation. Familiarity with failure triage using scan diagnosis tools. Soft Skills: Ability to work in a fast-paced, evolving environment Self-driven, detail-oriented, execution-focused. Team player with the ability to work across international teams.

Lead and develop Physical Design Methodologies emphasizing on best-in-class Methodologies for corporate wide digital flows using EDA tools from leading vendors like Cadence, Synopsys and Mentor Graphics Work with global CAD methodology development team to automate and integrate the above CAD flows for centralized deployment Provide strong technical expertise and consultations on place and route and rail analysis EDA flows to ADI s Business Units and ensure successful tapeouts of their products Desired Skills: Expertise in developing CAD Solutions in the areas of physical design using Cadence, Synopsys or Mentor Graphics EDA tool suite Sound Knowledge in Cadence EDA place and route tools (Innovus) Experience in overall digital implementation flows (RTL to GDS II) and has a well-proven track record of being involved in successful multi-million gate SOC design tapeouts in nanometer technology Experience in low power design and implementation methodologies is desirable Experience in working on sub 10nm technologies is desirable Strong experience in automation of methodologies/solution using TCL, Python, PERL and Tk Debugging experience to debug vendor tool problems and interacting with designers to help tackle their problems Possess excellent interpersonal and communication skills to collaborate and influence design development groups across the globe.

Skills : Calibre,ICC2,Perl,TCL Total vacancies : 3 Experience on EMIR analysis for multiple modes, including; static and dynamic with/without functional vectors Should have expertise in understanding and debugging EMIR issues in a block level. Power analysis for the blocks. Experience on Floor-planning, Place & route, power and clock distribution, pin placement. In-depth knowledge on industry leading tools like Redhawk, Olympus/ICC2, Primetime, and Calibre Knowledge of package modeling, package and chip level analysis is added advantage Good understanding of Physical design verification using Calibre. Knowledge of Synthesis and DFT is added advantage. Prior experience with 16nm or finer geometries is a plus. Proficient use of tcl/Perl Must have good communication skills and self-driven individual

ADI is seeking a skilled Digital Design (Synthesis/STA) Engineer to support ASIC product development worldwide. This role involves close collaboration with Design-for-Test (DFT) engineers and Physical Design engineers to deliver comprehensive design implementation solutions for our business units. This position is part of ADI s Engineering Enablement group, with a strong focus on digital design implementation services. The ideal candidate is goal-oriented, self-driven, and upholds high professional standards while thriving in a team-oriented environment. Key Responsibilities Execute RTL Qualification, Logic Synthesis, Static Timing Analysis, and Equivalence Checking Develop and verify constraints, perform Timing/SI Closure, Power Analysis/Optimization, and implement low-power designs Collaborate closely with Design, DFT, and Physical Design engineers to provide front-end implementation services and support EDA tools and flows Maintain a deep understanding of automation flows and EDA tool functionalities Develop and refine Perl, Tcl, Ruby, and Shell scripts for process automation Minimum Qualifications MSEE with 1+ years or BSEE with 3+ years of industry experience in synthesis, STA, and equivalence checking Expert proficiency in DesignCompiler/Genus, PrimeTime/Tempus, and Conformal Experience in low-power/UPF implementation and Spyglass RTL checkers (preferred) Knowledge in timing/SI closure, DFT, and design verification (preferred) Familiarity with Verilog Strong programming/scripting skills in Perl, Tcl, Ruby, Shell, Java, Scala, and Python Excellent problem-solving, written, and verbal communication skills

THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities: Physical Design Implementation: Translate complex CDNA and RDNA graphics IP RTL designs into optimized physical layouts. Utilize industry-leading EDA tools for synthesis, place-and-route (PnR), and physical verification processes to take the design thru mock-taepout Performance Optimization: Focus on power, performance, and area (PPA) optimization to meet the stringent requirements of high-performance graphics and compute products. Collaborate with architecture and front-end design teams to align RTL design with physical constraints and objectives. Verification and Timing Closure: Conduct static timing analysis (STA) to ensure robust timing closure and sign-off for graphics IP. Implement and verify design rule checks (DRC), layout versus schematic checks (LVS), and power grid analysis tailored to CDNA and RDNA requirements. Collaboration and Communication: Work closely with cross-functional teams, including architects, RTL designers, and verification engineers to ensure seamless integration and functionality of graphics IP cores. Provide feedback and suggest improvements to design methodologies and processes to push the technology envelope further. Documentation and Reporting: Maintain comprehensive design documentation, methodologies, and updates. Prepare detailed reports on design progress, performance metrics, and any technical challenges encountered. PREFERRED EXPERIENCE: Domain Expertise: Experience with working on complex design and optimizing for performance, power, and area. Technical Proficiency: Proven track record in RTL synthesis, place-and-route (PnR), and static timing analysis (STA) for complex IP cores. Proficiency with industry-leading EDA tools, such as Synopsys Design Compiler, Cadence Innovus, and timing analysis tools like PrimeTime. Experience with low-power design methodologies and techniques for high-performance graphics IP. Design and Verification: Successful completion of full-chip sign-off, including design rule checks (DRC) and layout versus schematic (LVS) checks. Strong skills in signal integrity analysis, including crosstalk and IR drop evaluations. Process Technology: Experience working with advanced semiconductor process nodes (e.g., 7nm, 5nm, or below). Knowledge of process-related challenges and optimization techniques for graphics applications. Scripting and Automation: Proficiency in scripting languages such as Perl, Python, or TCL to automate design flows and improve efficiency. Experience developing and maintaining scripts for design rule checks and optimization processes. Problem-Solving and Innovation: Demonstrated ability to solve complex design challenges using innovative approaches. A track record of contributing to the improvement of design techniques and methodologies in a graphics-focused engineering team. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #

What You'll Be Doing : - In this position, you will expect to lead all block/chip level PD activities. - PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. - Work in collaboration with design team for addressing design challenges. - Help team members in debugging tool/design related issues. - Constantly look for improvement in RTL2GDS flow to improve PPA. - Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. - Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. Minimum Qualifications : - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. What We Need To See : - Strong experience in Physical Design. - Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. - Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. - Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. - Well versed with timing constraints, STA and timing closure. - Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. - Ability to multi-task and flexibility to work in global environment. - Good communication skills and strong motivation, Strong analytical & Problem solving skills. - Proficiency using Perl, Tcl, Make scripting is preferred. - Widely considered to be one of the technology worlds most desirable employers, offers highly competitive salaries and a comprehensive benefits package. Require candidates with a minimum of 5 years of relevant experience

Hiring Freshers Kickstart Your Career in VLSI At PRSsemicon Technologies, we are shaping the future of semiconductor innovation by building a Global Capability Development Centre. We are looking for fresh graduates passionate about VLSI domains to join our team. Through structured training and hands-on experience, we ensure you gain the technical expertise and industry-relevant skills required to succeed in this dynamic field. Your Journey with Us: Comprehensive Training Gain in-depth knowledge of VLSI design, verification, emulation, DFT, physical design, and analog design based on project needs. Hands-on Experience Work with industry-standard tools and methodologies. Expert Guidance Learn from seasoned professionals and build practical expertise. Live Project Transition Successfully complete training and contribute to real-world chip design projects. What We Look For: Strong fundamentals in Digital Electronics. Eagerness to learn and build competency before taking on project responsibilities. Passion for VLSI design and a commitment to a long-term career in semiconductors. Why Join PRSsemicon? Be part of Indias thriving semiconductor industry. Learn from experienced professionals in a structured training environment. Get hands-on exposure to cutting-edge chip design projects. Headquarter: Chennai Mode: Offline/Online/Hybrid (as per project requirements) Eligibility: B. Tech/M. Tech in ECE, EEE, E & I, VLSI, or related fields Year of passing out: From 2022 and below (2021, 2020.. ) will be considered Apply Now & Shape the Future of VLSI with Us!

Job Category: Engineer Job Type: Full Time Job Location: Bangalore Join Mettlesemi s DFT design team to develop next-gen chips with a revolutionary architecture. Contribute to a multifaceted DFT approach, including architecture definition, logic design, verification, test pattern generation, and chip bring-up. Work in a dynamic, open, and fast-paced environment on cutting-edge silicon chip technologies. Shape the future of chips for top-notch clients. KEY JOB RESPONSIBILITIES: Senior DFT Engineer pivotal in device lifecycle, from definition to mass production. Collaborate with VLSI groups (chip design, verification, backend, test, and reliability). Develop, implement, and verify DFT on complex SOCS. Work closely with architecture team for DFT understanding. Ensure DFT design rules compliance with design teams. Collaborate with physical design team to meet DFT requirements. Expertise in SOC-level DFT techniques (ATPG, MBIST, JTAG, boundary scan). BASIC QUALIFICATIONS 6+ years chip design experience. 4+ years as a DFT engineer in a semiconductor company. Bachelor s/Master s in Electrical/Electronics Engineering. Strong post-silicon DFT bring-up and debug experience. Hands-on experience with multi-vendor DFT tools. Proficiency in ATPG tools (Mentor TK). Exposure to static timing analysis; timing closure. Excellent scripting skills in Perl/Tcl/Tk/Python. Knowledge of DFT technologies (JTAG, MBIST, Scan). Experience with RTL Coding (Verilog, System Verilog, VHDL). PREFERRED QUALIFICATIONS: Expertise in DFT methodologies (scan insertion, scan compression, boundary scan, memory BIST). Experience with DFT tools (Tessent, ATPG, MBIST, JTAG). Proficiency in Shell/Perl/Tcl and other scripting languages. Familiarity with ATE. Chip design, Verilog, and System Verilog. Verification, UVM methodology. ATPG tools, scan insertion tools, gate-level simulations. Static timing analysis. Scripting (Perl/Tcl). INTERPERSONAL SKILLS: Energetic, self-motivated Leader and Team player Proactive, detail-oriented, and quality-focused. Strong communication and reporting skills. Ability to collaborate with cross-national partners

Job Category: Design Job Type: Full Time Job Location: Bangalore About Us: Mettlesemi Systems and Technologies Pvt Ltd, based in Bengaluru, specializes in providing embedded systems, silicon solutions and related services. We have strong partnerships with top oplayers in the Semiconductor and Embedded Systems domain, across product development and prototyping. The Role: Mettlesemi is looking for exceptional engineers and engineering leaders to join our SOC development team to develop cutting-edge products within disruptive system architecture. You will have the oppertunity to work on the latest technologies in silicon chip design within a dynamic, open, and fast-peaced environment and develop the next generation of chips based on revolutionary architecture for our top-notch clients. Key Responsiblities: We are looking for talented Senior engineers to join our top-tier teams and participate in design and verification activities working on next-generation products, starting from the identification and definition of project requirements, architecture, and feature development. As a Design Engineer and integral part of the project team, your responsibilities will encompass the development of intricate Microarchitecture, Logic Design, Synthesis, Timing Closure, and Formal Verification using Formality. Collaboration with the Design Verification Team, the DFT Team, the Physical Design Team and other stakeholder teams will be a key aspect of your role. This presents a unique opportunity for you to make a significant impact across the entire product lifecycle. In this role, you will work in a team developing SoCs to be deployed in a range of products/applications. You will integrate industry-standard and custom hardware IP and subsystems into SoCs and will work closely with System Architects, SoC architects, IP developers, and physical design teams to develop SoCs that meet the power, performance, and area goals for these products/applications. BASIC QUALIFICATIONS 6+ years of experience in chip design. 5+ years or more of practical semiconductor design experience. Proficiency in Verilog/System Verilog. Fluent in scripting languages (TCL, Python). BE degree in Computer Engineering/BS Computer Science/Electrical Engineering. Excellent verbal and written communication skills. Strong collaboration and teamwork skills, ability to contribute to diverse and inclusive teams. PREFERRED SKILLS/EXPERIENCE Experience with the full SOC cycle Synthesis/STA/CDC/Lint. Experience with successful tape-outs of complex, high- volume SoCs in advanced design nodes. Experience with Design Automation. Experience in Designing protocols such as AMBA, LPDDR, DDR4 Strong working knowledge of Network on Chip (NOC), Coherent, and non-Coherent fabrics.

Basic Section No. Of Position 1 Grade ST Level Staff Organisational Industry -- Function -- Skills Skill Admin Transportation Operations Vehicle Tracking Vehicle Maintenance Bill Processing Logistics Consulting General Administration Onboarding RTO Management Road Safety Audits MIS & Analytics Safety WCM-Interwoven Interpersonal Abilities Coordinating Activities Communication Skills Drafting Official Responses Document Drafting Liaison Minimum Qualification Graduate Diploma in Business Management PGD in Business Administration Bachelor"s Of Hospitality Mgt CERTIFICATION No data available About The Role Job Purpose Role Objective To efficiently manage the planning, deployment, and coordination of company-hired transport services while ensuring adherence to road safety and statutory compliance. The role also extends to overseeing plant general administrative services such as event management, pantry services, and office infrastructure support. Key Responsibilities Plan and deploy company-hired vehicles for employee and guest movement, including timely pick-up/drop at railway stations and airports. Coordinate with the Purchase Team for vehicle hiring requirements through approved transporters. Ensure all deployed vehicles comply with road safety norms and statutory regulations (permits, insurance, driver license, etc.). Monitor and schedule regular vehicle maintenance in coordination with the respective transporter to avoid breakdowns or service delays. Maintain a vehicle deployment log and analyze usage patterns for optimization. Verify and scrutinize transporter bills and ensure timely submission to the accounts department for processing payments. Manage event arrangements within the plant premises, including logistics and coordination with vendors. Oversee pantry operations to ensure cleanliness, hygiene, and timely service across all departments. Coordinate procurement and placement of office furniture in consultation with stakeholders. Ensure proper seating arrangements for employees, especially during transfers, onboarding, or departmental relocations. Maintain an updated asset register for administrative utilities and coordinate repairs/replacements as needed.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Principal Duties and Responsibilities: 12+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains"“ LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux "“ Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 12+ years Hardware Engineering experience or related work experience. 12+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

"> Search Jobs Find Jobs For Where Search Jobs ASIC Physical Design, Sr Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 4940 Remote Eligible No Date Posted 23/08/2024 Has a strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience in tools like DC, ICC2, PT-SI is a definite advantage. Should be a strong team player, excellent communicator as the role involves daily technical interaction with local, US counter parts. He/She will be part of SNPS DDR/HBM/UCIe/Die-to-Die IP implementation team and responsible for the implementation and power signoff of world class DDRs at the cutting edge technology nodes. Timing closure above ~2GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR power signoff would be an added advantage. Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality. Typically requires a minimum of 9+ years of related experience. Possesses a full understanding of specialization area plus working knowledge of multiple related areas. Independently resolves a wide range of issues in creative ways on a regular basis. Customarily exercises independent judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is independent and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job. Frequently networks with senior internal and external personnel in own area of expertise. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production. As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs. This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug. You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness. Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability from early DFT architecture planning to high-volume silicon bring-up and yield ramp. Key job responsibilities Key job responsibilities Lead development & implementation of DFT architecture including system level DFT for a full chip Write and guide others in writing design flow and project documentation. Own DFT planning, milestone tracking, and cross-functional checklist reviews. Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists. Review and sign-off SoC level DFT mode timing closure using static timing analysis Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon Keep informed on and introduce new technology into Design-for-Test process as appropriate. Education: BS/BE or MS/ME in Electrical Engineering, Computer Engineering, or related field. Experience: 15+ years in SoC/ASIC DFT, including 3+ years Leading DFT. Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production. DFT Architecture Expertise: Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including: Scan architecture, compression, and ATPG implementation for high fault coverage and test quality. MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration. IEEE 1149.x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures. DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths. RTL and gate-level debug, including mismatch triage and simulation correlation. Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation. Tool Proficiency: Deep hands-on experience with Tessent / Industry Std EDA tools, including: IJTAG ICL extraction and PDL modeling. DFT logic insertion, pattern generation, and diagnostics. Design Background: Experience in writing verilog/system verilog RTL related to DFT logic design. ATE Test Readiness: Lead DFT-to-ATE handoff, including: Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets. Pattern validation, format conversion, and debugging across wafer sort and final test. Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements. Silicon Debug: Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis. Automation Skills: Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl. Collaboration: Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing. Execution Excellence: Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success. Leadership: Led multi-site/global DFT teams, mentoring engineers and managing design reviews. Drove design-for-test planning in collaboration with customers or design services partners. Technical Depth: Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies. Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues. Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division) s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers. The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & JTAG. The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug. Strong problem solving & debugging skills are a must. Expertise in scripting languages such as perl, shell, etc. is an added advantage. Experience with either Mentor Graphics DFT tools (TestKompress, Fastscan) or Synopsys DFT tools (DFTMax, Tetramax) is highly desirable. The candidate should have worked with team across multiple geographies. The candidate should be able to handle his/her work independently and also supervise the work of other team members as required. The candidate should possess excellent communication skills. Educational qualification & Experience Level : Bachelor s degree with 8+ years of relevant experience or Master s degree with 6+ years of relevant experience Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division) s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics It involves working with the Physical Design & STA team for DFT mode timing closure The role could also involve direct interaction with external customers The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & JTAG The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug Strong problem solving & debugging skills are a must Expertise in scripting languages such as perl, shell, etc is an added advantage Experience with either Mentor Graphics DFT tools (TestKompress, Fastscan) or Synopsys DFT tools (DFTMax, Tetramax) is highly desirable The candidate should have worked with team across multiple geographies The candidate should be able to handle his/her work independently and also supervise the work of other team members as required The candidate should possess excellent communication skills Educational qualification & Experience Level : Bachelor s degree with 8+ years of relevant experience or Master s degree with 6+ years of relevant experience

As our ideal candidate, you are a seasoned professional with a deep understanding of CMOS analog and mixed-signal Layout Design Engineering. You thrive in a collaborative environment and are passionate about pushing the boundaries of technology. With over 5 years of experience, you have honed your skills in designing complex PLLs, VCOs, charge pumps, and high-speed digital circuits Layout. You are detail-oriented, capable of coordinating with various teams, and have a proven track record of delivering high-quality designs. Your strong foundation in electrical engineering, combined with your innovative mindset, allows you to tackle diverse problems creatively and effectively. With excellent communication skills, you can articulate complex technical concepts to both technical and non-technical stakeholders, ensuring seamless collaboration and project success. What You ll Be Doing: Collaborate with cross-functional teams to develop and implement layout designs for analog and mixed-signal (A&MS) integrated circuits in PLL and other IP Create and optimize layout designs using industry-standard EDA tools. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Define, design and develop complex RF clock path Participate in design reviews and provide feedback to improve design quality. Work closely with circuit designers to understand design specifications and constraints. Contribute to the development and enhancement of layout design methodologies and best practices. Stay updated with the latest industry trends and advancements in A&MS layout design. The Impact You Will Have: Ensure the highest quality and performance of our analog and mixed-signal integrated circuits. Drive innovation by developing cutting-edge layout designs that push the boundaries of technology. Enhance the manufacturability and reliability of our products through meticulous design and verification processes. Contribute to the overall success of our projects by providing valuable feedback during design reviews. Improve design methodologies and best practices, fostering a culture of continuous improvement. Support the growth and development of junior engineers by sharing your expertise and knowledge. What You ll Need: Bachelors or Masters degree in Electrical Engineering or a related field. 7+ years of experience in A&MS layout design for integrated circuits. Hands physical design experience of passive elements used in PLL RC filter, LC oscillator Basic knowledge of PLL operating blocks Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented env Who You Are: Innovative thinker with a passion for technology and problem-solving. Excellent communicator, capable of articulating complex concepts clearly. Detail-oriented with a strong focus on quality and precision. Collaborative team player who thrives in a dynamic work environment. Adaptable and able to manage multiple priorities effectively

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. You have a proven track record of working on advanced nodes under 5nm and are proficient in low-power, high-performance design. Your familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. You are adept at scripting languages such as TCL, Perl, and Python, and hold a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience. You thrive in a dynamic environment, constantly seeking to push the boundaries of technology and improve quality of results. Your ability to work both independently and collaboratively makes you an invaluable asset to any team. What You ll Be Doing: Developing innovative methodologies for implementing high-performance CPUs, GPUs, and interface IPs. Utilizing advanced technologies and tool features to enhance quality of results and streamline the implementation process. Contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs. Working with industry-leading Synopsys tools such as RTLA and Fusion Compiler to solve critical design challenges. Collaborating with a global team to stay ahead of technological advancements and design complexities. Driving continuous improvement in PPA and turnaround time (TAT) metrics. The Impact You Will Have: Advancing the state-of-the-art in high-performance core and IP implementation. Enhancing the performance and efficiency of Synopsys design methodologies and tools. Enabling the development of cutting-edge semiconductor technologies at advanced nodes. Contributing to the successful delivery of high-quality, high-performance IPs to the market. Driving innovation and pushing the boundaries of what is possible in chip design. Supporting Synopsys mission to lead in chip design, verification, and IP integration. What You ll Need: Deep knowledge of synthesis, timing closure, power optimization, and constraints management. Experience with low-power, high-performance design at advanced nodes under 5nm. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX. Familiarity with scripting languages such as TCL, Perl, and Python. BS or MS in Electrical Engineering or a related field with 9+ years of relevant experience.

Develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. Work with leading edge designs and teams to drive the industry best PPA for IP designs. Evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO s. Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. Work as a liaison between EDAG tool and IP design teams. Continuously improve and refine design processes to enhance efficiency and performance. The Impact You Will Have: Drive innovation in high-speed digital IP core and Subsystem development. Enhance the efficiency and effectiveness of our design and verification processes. Contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. Ensure the highest quality standards in the design and implementation of our products. Facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. Support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements. What You ll Need: BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. Direct hands-on experience with Primetime, Primepower/PTPX, or industry equivalent tools. Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. Good analysis, debugging, and problem-solving skills. Solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings. Familiarity with other Synopsys tools such as StarRC, ICV, and experience with Ansys RedHawk is a plus. Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus

Driving the physical implementation of high-speed interface IPs and test-chips from RTL to GDS. Managing timing and physical sign-off to ensure successful project tape-outs. Collaborating with multiple functional groups, including front-end, analog, and CAD teams. Focusing on advanced SerDes developments, including the latest 56/112G PAM4 standards. Leading the physical design team to ensure on-time delivery of projects. Utilizing your software and scripting skills to enhance CAD automation methods. The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything. Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements. Reducing the risk and time-to-market for differentiated products. Driving technological innovation through advanced SerDes development. Enhancing Synopsys reputation as a leader in chip design and verification. Supporting the companys mission to power the world s most advanced technologies for chip design and software security. What You ll Need: 10+ years of physical design experience with recent contributions to project tape-outs. Intimate understanding of the full design cycle from RTL to GDSII, including chip level. Experience with advanced FinFET nodes, TSMC 16 nanometer or below. Solid understanding of IC design, implementation flows, and methodologies for deep submicron design. Proven track record for technical steering of physical design teams for on-time delivery. Who You Are: Excellent communicator with the ability to engage with peer groups and customers. Autonomous and capable of making timely judgments. Proficient in software and scripting skills (Perl, Tcl, Python). Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs. Able to travel internationally as required

Owning the complete physical implementation process at both block and chip levels. Delivering timing clean blocks and chip-level designs that meet design targets. Ensuring DRC, LVS, and IR closure for all designs. Setting up and evaluating all aspects of the physical design flow, including place and route, timing, PV, and IR. Collaborating closely with the frontend design team to resolve design issues. Executing project responsibilities from start to completion, contributing to moderately complex aspects of the project. The Impact You Will Have: Ensuring the delivery of high-quality, timing-clean designs that meet industry standards. Driving innovation in physical design methodologies and processes. Contributing to the development of cutting-edge technologies that shape the future. Enhancing the overall efficiency and effectiveness of the design team. Providing mentorship and guidance to junior engineers, fostering a culture of continuous learning and improvement. Strengthening Synopsys position as a leader in the semiconductor industry through your expertise and contributions. What You ll Need: MSEE/BSEE with 6+ years of related experience in ASIC physical design. In-depth understanding of physical design specialization, with working knowledge of one other related area. Strong problem-solving skills and creativity in resolving design issues. Experience in scripting using Tcl and Perl. Ability to execute project responsibilities independently and contribute to team-driven projects. Who You Are: Detail-oriented and committed to delivering high-quality work. Collaborative and able to work effectively in a team environment. Proactive and able to take ownership of tasks and projects. Excellent communicator, capable of networking with senior personnel. Mentor and guide to junior peers, sharing knowledge and expertise.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: Strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience in tools like DC, ICC2, PT-SI,FC is a definite advantage. Should be a strong team player, excellent communicator as the role involves daily technical interaction with local, US counter parts. What You ll Be Doing: He/She will be part of SNPS DDR/HBM/Ucie IP implementation team and responsible for the implementation and integration of world class DDRs at the cutting-edge technology nodes. Timing closure above ~4GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/HBI timing closure, implementation would be an added advantage. Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality. Who You Are: Typically requires a minimum of 6+ years of related experience after the post graduation. Possesses a full understanding of specialization area plus working knowledge of multiple related areas. A team player Independently resolves a wide range of issues in creative ways on a regular basis. Customarily exercises independent judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is independent and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job.

Implementing and power signoff of world-class DDRs at cutting-edge technology nodes. Achieving timing closure above ~2GHz and integrating mixed signal macro IPs. Building efficient clock trees with very tight skew balancing. Providing regular updates to your manager on project status. Guiding junior peers with aspects of their job and contributing to their development. Representing the organization on business unit and/or company-wide projects. The Impact You Will Have: Driving the implementation of cutting-edge DDR technology, contributing to the advancement of high-performance computing. Ensuring the power efficiency and performance of our silicon chips, crucial for our competitive edge. Enhancing the reliability and integration of mixed signal macro IPs. Contributing to the overall success and innovation of Synopsys IP solutions. Mentoring junior engineers, fostering a culture of continuous learning and improvement. Representing Synopsys in key projects, influencing the direction and success of our initiatives. What You ll Need: Minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in tools like DC, ICC2, StarRC, and PT-SI. Strong understanding of timing closure, power signoff, and mixed signal macro IP integration. Experience with DDR power signoff and clock tree building. Excellent problem-solving and analytical skills. Who You Are: A strong team player with excellent communication skills. Independent and collaborative, capable of working with minimal supervision. Creative and innovative, able to develop unique solutions to complex problems. Detail-oriented and organized, ensuring high-quality project outcomes. Passionate about continuous learning and professional growth.