DFT Engineer (MBIST) in Bangalore, KA, India
Description
Invent the future with us.
Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing.
By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow.
Join us at Ampere and work alongside a passionate and growing team we d love to have you apply. Come invent the future with us.
About the role:
What youll achieve:
- DFT features like jtag/ijtag, regular & shared bus based MBIST insertion for advanced nodes.
- Verification of jtag/ijtag, MBIST features in RTL and GLS
- Post silicon debug and diagnosis MBIST related issues
- Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys)
- STA DFT Test mode timing constraint development and analysis
- In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools
- ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data
About you:
- Bachelors degree & 3 years of related experience or Masters degree & 2 years of related experience
- Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non-repairable memories using Electrical fuses
- Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions.
- Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions
- Experience in implementing jtag/ijtag features.
- Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level
- Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow
- Experience in working with physical design teams to support STA constraints, reviewing timing reports
- Expert in using silicon debug/diagnosis tools to root cause silicon bring up and production test issue
- Experience in setting up and running Scan DRC flows in RTL.
- Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl
- Experience in revision control systems like GIT, perforce etc.
What we ll offer:
At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits.
Benefits highlights include:
- Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work.
- Generous paid time off policy so that you can embrace a healthy work-life balance
- Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day.
And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.
Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.
